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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 7/8] drm/i915/psr: Include PSR_PERF_CNT in debugfs output on all platforms
Date: Tue, 28 Mar 2023 12:30:41 +0300	[thread overview]
Message-ID: <20230328093042.7469-8-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20230328093042.7469-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The fact that DC states reset the PSR perofrmance counter
is no reason not to include it in the debug output.
But let's keep the comment there to remind people about
that caveat.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 142cd174475e..807bf1b77ca7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2819,12 +2819,10 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp)
 	/*
 	 * SKL+ Perf counter is reset to 0 everytime DC state is entered
 	 */
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-		val = intel_de_read(dev_priv,
-				    EDP_PSR_PERF_CNT(intel_dp->psr.transcoder));
-		seq_printf(m, "Performance counter: %u\n",
-			   REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val));
-	}
+	val = intel_de_read(dev_priv,
+			    EDP_PSR_PERF_CNT(intel_dp->psr.transcoder));
+	seq_printf(m, "Performance counter: %u\n",
+		   REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val));
 
 	if (psr->debug & I915_PSR_DEBUG_IRQ) {
 		seq_printf(m, "Last attempted entry at: %lld\n",
-- 
2.39.2


  parent reply	other threads:[~2023-03-28  9:31 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-28  9:30 [Intel-gfx] [PATCH 0/8] drm/i915: (mostly) PSR related register cleanups Ville Syrjala
2023-03-28  9:30 ` [Intel-gfx] [PATCH 1/8] drm/i915: Fix up whitespace in some display chicken registers Ville Syrjala
2023-03-28  9:30 ` [Intel-gfx] [PATCH 2/8] drm/i915: Clean up various " Ville Syrjala
2023-03-28  9:30 ` [Intel-gfx] [PATCH 3/8] drm/i915/psr: Clean up PSR register defininitions Ville Syrjala
2023-03-28  9:30 ` [Intel-gfx] [PATCH 4/8] drm/i915/psr: Use intel_de_rmw() Ville Syrjala
2023-03-28  9:30 ` [Intel-gfx] [PATCH 5/8] drm/i915/psr: Define more PSR mask bits Ville Syrjala
2023-03-29 18:54   ` Ville Syrjälä
2023-03-28  9:30 ` [Intel-gfx] [PATCH 6/8] drm/i915/psr: Add a FIXME for the PSR vs. AUX usage conflict Ville Syrjala
2023-03-28  9:30 ` Ville Syrjala [this message]
2023-03-28  9:30 ` [Intel-gfx] [PATCH 8/8] drm/i915/psr: Sprinkle cpu_transcoder variables around Ville Syrjala
2023-03-28 21:19 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: (mostly) PSR related register cleanups Patchwork
2023-03-28 21:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-28 21:36 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-03-29 22:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: (mostly) PSR related register cleanups (rev2) Patchwork
2023-03-29 22:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-03-29 22:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-30 15:21 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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