From: Andrzej Hajda <andrzej.hajda@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Subject: [Intel-gfx] [CI DO_NOT_MERGE 2/3] drm/i915/gt: do not enable render and media power-gating on RPL-S
Date: Tue, 16 May 2023 15:36:45 +0200 [thread overview]
Message-ID: <20230516133646.3708898-2-andrzej.hajda@intel.com> (raw)
In-Reply-To: <20230516133646.3708898-1-andrzej.hajda@intel.com>
Multiple CI tests fails with forcewake timeouts. Disabling power
gating for render and media solves the issue.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/4983
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 0819576ffeb5df..c405b209e47922 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -126,6 +126,9 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
pg_enable =
GEN9_MEDIA_PG_ENABLE |
GEN11_MEDIA_SAMPLER_PG_ENABLE;
+ /* Testing */
+ else if (IS_ADLS_RPLS(gt->i915))
+ pg_enable = 0;
else
pg_enable =
GEN9_RENDER_PG_ENABLE |
--
2.34.1
next prev parent reply other threads:[~2023-05-16 13:37 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-16 13:36 [Intel-gfx] [CI DO_NOT_MERGE 1/3] drm/i915/mtl: do not enable render power-gating on MTL Andrzej Hajda
2023-05-16 13:36 ` Andrzej Hajda [this message]
2023-05-16 13:36 ` [Intel-gfx] [CI DO_NOT_MERGE 3/3] drm/i915/selftests: add forcewake_with_spinners tests Andrzej Hajda
2023-05-16 21:14 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL Patchwork
2023-05-16 21:14 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-05-16 21:38 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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