From: Andrzej Hajda <andrzej.hajda@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Andrzej Hajda <andrzej.hajda@intel.com>
Subject: [Intel-gfx] [CI DO_NOT_MERGE 1/3] drm/i915/mtl: do not enable render power-gating on MTL
Date: Wed, 17 May 2023 21:40:38 +0200 [thread overview]
Message-ID: <20230517194040.3857137-1-andrzej.hajda@intel.com> (raw)
Multiple CI tests fails with forcewake ack timeouts
if render power gating is enabled.
BSpec 52698 clearly states it should be 0 for MTL.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4983
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 908a3d0f2343f4..ebb2373dd73640 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -117,8 +117,9 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
GEN6_RC_CTL_RC6_ENABLE |
GEN6_RC_CTL_EI_MODE(1);
- /* Wa_16011777198 - Render powergating must remain disabled */
- if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
+ /* Wa_16011777198 and BSpec 52698 - Render powergating must be off */
+ if (IS_METEORLAKE(gt->i915) ||
+ IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
pg_enable =
GEN9_MEDIA_PG_ENABLE |
--
2.34.1
next reply other threads:[~2023-05-17 19:41 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-17 19:40 Andrzej Hajda [this message]
2023-05-17 19:40 ` [Intel-gfx] [CI DO_NOT_MERGE 2/3] drm/i915/gt: do not enable render and media power-gating on ADL Andrzej Hajda
2023-05-17 19:40 ` [Intel-gfx] [CI DO_NOT_MERGE 3/3] drm/i915/selftests: add forcewake_with_spinners tests Andrzej Hajda
2023-05-17 20:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL Patchwork
2023-05-17 20:22 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-05-17 20:43 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-05-18 18:44 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [CI,DO_NOT_MERGE,1/3] drm/i915/mtl: do not enable render power-gating on MTL (rev2) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-05-16 13:36 [Intel-gfx] [CI DO_NOT_MERGE 1/3] drm/i915/mtl: do not enable render power-gating on MTL Andrzej Hajda
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