[Intel-gfx] [PATCH 6/6] drm/i915/display: Enable global hist Selective fetch

[Arun R Murthy <arun.r.murthy@intel.com>]

This patch enables support for selective fetch in global histogram.
User can provide the selective fetch co-ordinates and only that region
will be used in generating the histogram.

Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 .../gpu/drm/i915/display/intel_global_hist.c  | 65 +++++++++++++++++++
 .../gpu/drm/i915/display/intel_global_hist.h  | 14 ++++
 2 files changed, 79 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_global_hist.c b/drivers/gpu/drm/i915/display/intel_global_hist.c
index 874d80d1e41b..13ec68463eec 100644
--- a/drivers/gpu/drm/i915/display/intel_global_hist.c
+++ b/drivers/gpu/drm/i915/display/intel_global_hist.c
@@ -31,6 +31,48 @@
 #include "intel_de.h"
 #include "intel_global_hist.h"
 
+#define MIN_SEGMENTS 32
+#define MAX_SEGMENTS 128
+
+static int intel_global_hist_calc_seg_size(struct drm_i915_private *dev_priv,
+		enum pipe pipe)
+{
+	uint32_t tmp, source_height;
+	uint16_t seg_size = MIN_SEGMENTS;
+
+	/* Get the pipe source height from the pipesr register */
+	tmp = intel_de_read(dev_priv, PIPESRC(pipe));
+	source_height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1;
+
+	while (seg_size <= source_height) {
+		if ((seg_size % source_height == 0) &&
+		   ((source_height / seg_size) < MAX_SEGMENTS))
+			break;
+		seg_size++;
+	}
+
+	return seg_size;
+}
+
+int intel_global_hist_sf_update_seg(struct drm_i915_private *i915,
+		enum pipe pipe, struct drm_rect *clip)
+{
+	uint16_t seg_size;
+
+	seg_size = intel_global_hist_calc_seg_size(i915, pipe);
+	if (!seg_size)
+		return -EINVAL;
+
+	intel_de_rmw(i915, DPST_SF_SEG(pipe),
+		     DPST_SF_SEG_SIZE_MASK | DPST_SF_SEG_START_MASK |
+		     DPST_SF_SEG_END_MASK,
+		     DPST_SF_SEG_SIZE(seg_size) |
+		     DPST_SF_SEG_START((clip->y2/seg_size) * seg_size) |
+		     DPST_SF_SEG_END((clip->y1/seg_size) * seg_size));
+
+	return 0;
+}
+
 static int intel_global_hist_get_data(struct drm_i915_private *i915,
 		enum pipe pipe)
 {
@@ -258,6 +300,29 @@ int intel_global_hist_set_iet_lut(struct intel_crtc *intel_crtc, u32 *data)
 	return 0;
 }
 
+int intel_global_hist_sf_en(struct drm_i915_private *i915,
+		enum pipe pipe, struct drm_rect *clip)
+{
+	struct intel_crtc *intel_crtc = to_intel_crtc(
+			drm_crtc_from_index(&i915->drm, pipe));
+	struct intel_global_hist *global_hist = intel_crtc->global_hist;
+	uint32_t dpstsfctl;
+
+	/* If DPST is not enabled, enable it first */
+	if (!global_hist->enable)
+		intel_global_hist_enable(intel_crtc);
+
+	/* Program dpst selective fetch */
+	dpstsfctl = intel_de_read(i915, DPST_SF_CTL(pipe));
+	dpstsfctl |= DPST_SF_CTL_ENABLE;
+	intel_de_write(i915, DPST_SF_CTL(pipe), dpstsfctl);
+
+	/* Program the segment size */
+	intel_global_hist_sf_update_seg(i915, pipe, clip);
+
+	return 0;
+}
+
 void intel_global_hist_deinit(struct intel_crtc *intel_crtc)
 {
 	struct intel_global_hist *global_hist = intel_crtc->global_hist;
diff --git a/drivers/gpu/drm/i915/display/intel_global_hist.h b/drivers/gpu/drm/i915/display/intel_global_hist.h
index c6621bf4ea61..827c61badf66 100644
--- a/drivers/gpu/drm/i915/display/intel_global_hist.h
+++ b/drivers/gpu/drm/i915/display/intel_global_hist.h
@@ -82,6 +82,20 @@
 #define GLOBAL_HIST_GUARDBAND_PRECISION_FACTOR 10000   // Precision factor for threshold guardband.
 #define GLOBAL_HIST_DEFAULT_GUARDBAND_DELAY 0x04
 
+#define _DPST_SF_CTL_A					0x490D0
+#define _DPST_SF_CTL_B					0x491D0
+#define DPST_SF_CTL(pipe)				_MMIO_PIPE(pipe, _DPST_SF_CTL_A, _DPST_SF_CTL_B)
+#define DPST_SF_CTL_ENABLE				(1 << 31)
+#define _DPST_SF_SEG_A					0x490D4
+#define _DPST_SF_SEG_B					0x491D4
+#define DPST_SF_SEG(pipe)				_MMIO_PIPE(pipe, _DPST_SF_CTL_A, _DPST_SF_CTL_B)
+#define DPST_SF_SEG_START_MASK				REG_GENMASK(30, 24)
+#define DPST_SF_SEG_START(val)				REG_FIELD_PREP(DPST_SF_SEG_START_MASK, val)
+#define DPST_SF_SEG_END_MASK				REG_GENMASK(22, 16)
+#define DPST_SF_SEG_END(val)				REG_FIELD_PREP(DPST_SF_SEG_END_MASK, val)
+#define DPST_SF_SEG_SIZE_MASK				REG_GENMASK(15, 0)
+#define DPST_SF_SEG_SIZE(val)				REG_FIELD_PREP(DPST_SF_SEG_SIZE_MASK, val)
+
 enum intel_global_hist_status {
 	INTEL_GLOBAL_HIST_ENABLE,
 	INTEL_GLOBAL_HIST_DISABLE,
-- 
2.25.1