From: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Cc: jani.nikula@intel.com
Subject: [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision
Date: Tue, 12 Sep 2023 22:07:28 +0530 [thread overview]
Message-ID: <20230912163735.1075868-2-mitulkumar.ajitkumar.golani@intel.com> (raw)
In-Reply-To: <20230912163735.1075868-1-mitulkumar.ajitkumar.golani@intel.com>
From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Add helper to get the DSC bits_per_pixel precision for the DP sink.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/display/drm_dp_helper.c | 27 +++++++++++++++++++++++++
include/drm/display/drm_dp_helper.h | 1 +
2 files changed, 28 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c b/drivers/gpu/drm/display/drm_dp_helper.c
index 8a1b64c57dfd..5c23d5b8fc50 100644
--- a/drivers/gpu/drm/display/drm_dp_helper.c
+++ b/drivers/gpu/drm/display/drm_dp_helper.c
@@ -2323,6 +2323,33 @@ int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
}
EXPORT_SYMBOL(drm_dp_read_desc);
+/**
+ * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
+ * @dsc_dpcd: DSC capabilities from DPCD
+ *
+ * Returns the bpp precision supported by the DP sink.
+ */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
+{
+ u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
+
+ switch (bpp_increment_dpcd) {
+ case DP_DSC_BITS_PER_PIXEL_1_16:
+ return 16;
+ case DP_DSC_BITS_PER_PIXEL_1_8:
+ return 8;
+ case DP_DSC_BITS_PER_PIXEL_1_4:
+ return 4;
+ case DP_DSC_BITS_PER_PIXEL_1_2:
+ return 2;
+ case DP_DSC_BITS_PER_PIXEL_1_1:
+ return 1;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
+
/**
* drm_dp_dsc_sink_max_slice_count() - Get the max slice count
* supported by the DSC sink.
diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 3369104e2d25..6968d4d87931 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -164,6 +164,7 @@ drm_dp_is_branch(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
}
/* DP/eDP DSC support */
+u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
bool is_edp);
u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]);
--
2.25.1
next prev parent reply other threads:[~2023-09-12 16:43 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-12 16:37 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
2023-09-12 16:37 ` Mitul Golani [this message]
2023-09-13 4:37 ` [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision Kandpal, Suraj
2023-09-12 16:37 ` [Intel-gfx] [PATCH 2/8] drm/i915/display: Store compressed bpp in U6.4 format Mitul Golani
2023-09-13 4:42 ` Kandpal, Suraj
2023-09-12 16:37 ` [Intel-gfx] [PATCH 3/8] drm/i915/display: Consider fractional vdsc bpp while computing m_n values Mitul Golani
2023-09-12 16:37 ` [Intel-gfx] [PATCH 4/8] drm/i915/audio : Consider fractional vdsc bpp while computing tu_data Mitul Golani
2023-09-12 16:37 ` [Intel-gfx] [PATCH 5/8] drm/i915/dsc/mtl: Add support for fractional bpp Mitul Golani
2023-09-12 16:37 ` [Intel-gfx] [PATCH 6/8] drm/i915/dp: Iterate over output bpp with fractional step size Mitul Golani
2023-09-12 16:37 ` [Intel-gfx] [PATCH 7/8] drm/i915/dsc: Add debugfs entry to validate DSC fractional bpp Mitul Golani
2023-09-12 16:37 ` [Intel-gfx] [PATCH 8/8] drm/i915/dsc: Allow DSC only with fractional bpp when forced from debugfs Mitul Golani
2023-09-12 22:03 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC fractional bpp support (rev6) Patchwork
2023-09-12 22:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-12 22:21 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-09-13 6:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
2023-09-13 6:05 ` [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision Mitul Golani
2023-09-13 6:14 ` Kandpal, Suraj
2023-09-21 7:41 ` Jani Nikula
2023-09-22 12:05 ` Maxime Ripard
2023-09-11 5:05 [Intel-gfx] [PATCH 0/8] Add DSC fractional bpp support Mitul Golani
2023-09-11 5:05 ` [Intel-gfx] [PATCH 1/8] drm/display/dp: Add helper function to get DSC bpp prescision Mitul Golani
2023-09-11 8:53 ` Kandpal, Suraj
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230912163735.1075868-2-mitulkumar.ajitkumar.golani@intel.com \
--to=mitulkumar.ajitkumar.golani@intel.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
--cc=jani.nikula@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox