From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v3 0/4] drm/i915: Start cleaning up the DPLL ID mess
Date: Tue, 3 Oct 2023 23:06:16 +0300 [thread overview]
Message-ID: <20231003200620.11633-1-ville.syrjala@linux.intel.com> (raw)
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Start to clean up the mess around DPLL IDs a bit by removing
the nasty assumption that the index of the DPLL in the
arrays matches its ID. Fortunately we did have a WARN
i nthere to cathc mistakes, but better to not has such
silly assumptions i nthe first place.
There's still a lot of mess left since the DPLL IDs in
the hardware are a mess as well. Eg. the index of the
register instance often differs from the index used
to select the DPLL in clock routing thing. So we could
probably clean up more of that, perhaps by declaring
separate IDs for each PLL for each use case...
v2:
- the trivial patches were already merged
- introduce pll->index
- add another patch for for_each_shared_dpll()
- add another patch s/dev_priv/i915/
v3:
- deal with pll->index in debugfs code
- rebase due to other changes
Ville Syrjälä (4):
drm/i915: Stop requiring PLL index == PLL ID
drm/i915: Decouple I915_NUM_PLLS from PLL IDs
drm/i915: Introduce for_each_shared_dpll()
drm/i915: s/dev_priv/i915/ in the shared_dpll code
.../drm/i915/display/intel_display_debugfs.c | 9 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 965 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 26 +-
.../gpu/drm/i915/display/intel_pch_refclk.c | 7 +-
4 files changed, 522 insertions(+), 485 deletions(-)
--
2.41.0
next reply other threads:[~2023-10-03 20:06 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-03 20:06 Ville Syrjala [this message]
2023-10-03 20:06 ` [Intel-gfx] [PATCH v3 1/4] drm/i915: Stop requiring PLL index == PLL ID Ville Syrjala
2023-10-03 20:06 ` [Intel-gfx] [PATCH v3 2/4] drm/i915: Decouple I915_NUM_PLLS from PLL IDs Ville Syrjala
2023-10-03 20:06 ` [Intel-gfx] [PATCH v3 3/4] drm/i915: Introduce for_each_shared_dpll() Ville Syrjala
2023-10-03 20:06 ` [Intel-gfx] [PATCH v3 4/4] drm/i915: s/dev_priv/i915/ in the shared_dpll code Ville Syrjala
2023-10-03 20:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Start cleaning up the DPLL ID mess (rev3) Patchwork
2023-10-03 20:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-03 21:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-04 0:09 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-04 7:53 ` [Intel-gfx] [PATCH v3 0/4] drm/i915: Start cleaning up the DPLL ID mess Jani Nikula
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20231003200620.11633-1-ville.syrjala@linux.intel.com \
--to=ville.syrjala@linux.intel.com \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox