From: Jonathan Cavitt <jonathan.cavitt@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: andi.shyti@intel.com, jonathan.cavitt@intel.com,
saurabhg.gupta@intel.com, nirmoy.das@intel.com
Subject: [Intel-gfx] [RFC PATCH 10/10] drm/i915: Use selective tlb invalidations where supported
Date: Tue, 10 Oct 2023 11:46:41 -0700 [thread overview]
Message-ID: <20231010184641.2119129-11-jonathan.cavitt@intel.com> (raw)
In-Reply-To: <20231010184641.2119129-1-jonathan.cavitt@intel.com>
For platforms supporting selective tlb invalidations, we don't need to
do a full tlb invalidation. Rather do a range based tlb invalidation for
every unbind of purged vma belongs to an active vm.
Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: Fei Yang <fei.yang@intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
---
drivers/gpu/drm/i915/gt/intel_ppgtt.c | 2 +-
drivers/gpu/drm/i915/i915_vma.c | 14 +++++++++-----
drivers/gpu/drm/i915/i915_vma.h | 3 ++-
3 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
index d07a4f97b9434..b43dae3cbd59f 100644
--- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c
@@ -211,7 +211,7 @@ void ppgtt_unbind_vma(struct i915_address_space *vm,
return;
vm->clear_range(vm, vma_res->start, vma_res->vma_size);
- vma_invalidate_tlb(vm, vma_res->tlb);
+ vma_invalidate_tlb(vm, vma_res->tlb, vma_res->start, vma_res->vma_size);
}
static unsigned long pd_count(u64 size, int shift)
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index d09aad34ba37f..cb05d794f0d0f 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -1339,7 +1339,8 @@ I915_SELFTEST_EXPORT int i915_vma_get_pages(struct i915_vma *vma)
return err;
}
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb
+ u64 start, u64 size)
{
struct intel_gt *gt;
int id;
@@ -1355,9 +1356,11 @@ void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb)
* the most recent TLB invalidation seqno, and if we have not yet
* flushed the TLBs upon release, perform a full invalidation.
*/
- for_each_gt(gt, vm->i915, id)
- WRITE_ONCE(tlb[id],
- intel_gt_next_invalidate_tlb_full(gt));
+ for_each_gt(gt, vm->i915, id) {
+ if (!intel_gt_invalidate_tlb_range(gt, start, size))
+ WRITE_ONCE(tlb[id],
+ intel_gt_next_invalidate_tlb_full(gt));
+ }
}
static void __vma_put_pages(struct i915_vma *vma, unsigned int count)
@@ -2041,7 +2044,8 @@ struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async)
dma_fence_put(unbind_fence);
unbind_fence = NULL;
}
- vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb);
+ vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb,
+ vma->node.start, vma->size);
}
/*
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index e356dfb883d34..5a604aad55dfe 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -260,7 +260,8 @@ bool i915_vma_misplaced(const struct i915_vma *vma,
u64 size, u64 alignment, u64 flags);
void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
void i915_vma_revoke_mmap(struct i915_vma *vma);
-void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb);
+void vma_invalidate_tlb(struct i915_address_space *vm, u32 *tlb,
+ u64 start, u64 size);
struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async);
int __i915_vma_unbind(struct i915_vma *vma);
int __must_check i915_vma_unbind(struct i915_vma *vma);
--
2.25.1
next prev parent reply other threads:[~2023-10-10 18:57 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-10 18:46 [Intel-gfx] [RFC PATCH 00/10] drm/i915: Implement range-based TLB Jonathan Cavitt
2023-10-10 18:46 ` [Intel-gfx] [RFC PATCH 01/10] drm/i915: Add GuC TLB Invalidation device info flags Jonathan Cavitt
2023-10-10 18:46 ` [Intel-gfx] [RFC PATCH 02/10] drm/i915/guc: Add CT size delay helper Jonathan Cavitt
2023-10-10 18:46 ` [Intel-gfx] [RFC PATCH 03/10] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-10 18:46 ` [Intel-gfx] [RFC PATCH 04/10] drm/i915: No TLB invalidation on suspended GT Jonathan Cavitt
2023-10-10 18:46 ` [Intel-gfx] [RFC PATCH 05/10] drm/i915: No TLB invalidation on wedged GT Jonathan Cavitt
2023-10-10 18:46 ` [Intel-gfx] [RFC PATCH 06/10] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck Jonathan Cavitt
2023-10-10 18:46 ` [Intel-gfx] [RFC PATCH 07/10] drm/i915: Enable GuC TLB invalidations for MTL Jonathan Cavitt
2023-10-10 18:46 ` [Intel-gfx] [RFC PATCH 08/10] drm/i915: Define GuC Based TLB invalidation routines Jonathan Cavitt
2023-10-10 18:46 ` [Intel-gfx] [RFC PATCH 09/10] drm/i915: Add generic interface for tlb invalidation Jonathan Cavitt
2023-10-10 18:46 ` Jonathan Cavitt [this message]
2023-10-11 3:49 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Implement range-based TLB Patchwork
-- strict thread matches above, loose matches on Subject: below --
2023-10-10 18:44 [Intel-gfx] [RFC PATCH 00/10] " Jonathan Cavitt
2023-10-10 18:44 ` [Intel-gfx] [RFC PATCH 10/10] drm/i915: Use selective tlb invalidations where supported Jonathan Cavitt
2023-10-11 8:16 ` Tvrtko Ursulin
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