From: Jonathan Cavitt <jonathan.cavitt@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: janusz.krzysztofik@intel.com, andi.shyti@intel.com,
matthew.d.roper@intel.com, jonathan.cavitt@intel.com,
saurabhg.gupta@intel.com, chris.p.wilson@linux.intel.com,
nirmoy.das@intel.com
Subject: [Intel-gfx] [PATCH v15 6/7] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck
Date: Fri, 13 Oct 2023 15:14:18 -0700 [thread overview]
Message-ID: <20231013221419.2710833-7-jonathan.cavitt@intel.com> (raw)
In-Reply-To: <20231013221419.2710833-1-jonathan.cavitt@intel.com>
For the gt_tlb live selftest, when operating on the GSC engine,
increase the timeout from 10 ms to 200 ms because the GSC
engine is a bit slower than the rest.
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
---
drivers/gpu/drm/i915/gt/selftest_tlb.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_tlb.c b/drivers/gpu/drm/i915/gt/selftest_tlb.c
index 7e41f69fc818f..00b872b6380b1 100644
--- a/drivers/gpu/drm/i915/gt/selftest_tlb.c
+++ b/drivers/gpu/drm/i915/gt/selftest_tlb.c
@@ -136,8 +136,15 @@ pte_tlbinv(struct intel_context *ce,
i915_request_get(rq);
i915_request_add(rq);
- /* Short sleep to sanitycheck the batch is spinning before we begin */
- msleep(10);
+ /*
+ * Short sleep to sanitycheck the batch is spinning before we begin.
+ * FIXME: Why is GSC so slow?
+ */
+ if (ce->engine->class == OTHER_CLASS)
+ msleep(200);
+ else
+ msleep(10);
+
if (va == vb) {
if (!i915_request_completed(rq)) {
pr_err("%s(%s): Semaphore sanitycheck failed %llx, with alignment %llx, using PTE size %x (phys %x, sg %x)\n",
--
2.25.1
next prev parent reply other threads:[~2023-10-13 22:26 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-13 22:14 [Intel-gfx] [PATCH v15 0/7] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-13 22:14 ` [Intel-gfx] [PATCH v15 1/7] drm/i915: Add GuC TLB Invalidation device info flags Jonathan Cavitt
2023-10-13 22:14 ` [Intel-gfx] [PATCH v15 2/7] drm/i915/guc: Add CT size delay helper Jonathan Cavitt
2023-10-13 22:14 ` [Intel-gfx] [PATCH v15 3/7] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-13 22:14 ` [Intel-gfx] [PATCH v15 4/7] drm/i915: No TLB invalidation on suspended GT Jonathan Cavitt
2023-10-13 22:14 ` [Intel-gfx] [PATCH v15 5/7] drm/i915: No TLB invalidation on wedged GT Jonathan Cavitt
2023-10-13 22:14 ` Jonathan Cavitt [this message]
2023-10-13 22:14 ` [Intel-gfx] [PATCH v15 7/7] drm/i915: Enable GuC TLB invalidations for MTL Jonathan Cavitt
2023-10-13 23:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines Patchwork
2023-10-13 23:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-13 23:35 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-15 4:54 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-15 5:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines (rev2) Patchwork
2023-10-15 5:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-15 6:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-15 8:53 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-10-15 20:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Define and use GuC and CTB TLB invalidation routines (rev3) Patchwork
2023-10-15 20:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-15 20:40 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-15 22:04 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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