From: Sebastian Wick <sebastian.wick@redhat.com>
To: Uma Shankar <uma.shankar@intel.com>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
ville.syrjala@linux.intel.com, pekka.paalanen@collabora.com,
contact@emersion.fr, harry.wentland@amd.com, mwen@igalia.com,
jadahl@redhat.com, shashank.sharma@amd.com, agoins@nvidia.com,
joshua@froggi.es, mdaenzer@redhat.com, aleixpol@kde.org,
xaver.hugl@gmail.com, victoria@system76.com, daniel@ffwll.ch,
quic_naseer@quicinc.com, quic_cbraga@quicinc.com,
quic_abhinavk@quicinc.com, arthurgrillo@riseup.net,
marcan@marcan.st, Liviu.Dudau@arm.com, sashamcintosh@google.com,
sean@poorly.run
Subject: Re: [PATCH 08/28] drm: Add Color lut range attributes
Date: Tue, 13 Feb 2024 13:04:04 +0100 [thread overview]
Message-ID: <20240213120404.GB1372043@toolbox> (raw)
In-Reply-To: <20240213064835.139464-9-uma.shankar@intel.com>
On Tue, Feb 13, 2024 at 12:18:15PM +0530, Uma Shankar wrote:
> This defines a new structure to define color lut ranges,
> along with related macro definitions and enums. This will help
> describe segmented lut ranges/PWL LUTs in the hardware.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
> ---
> include/uapi/drm/drm_mode.h | 58 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
> index af67f32e0087..376498715d0e 100644
> --- a/include/uapi/drm/drm_mode.h
> +++ b/include/uapi/drm/drm_mode.h
> @@ -1014,6 +1014,64 @@ struct hdr_output_metadata {
> DRM_MODE_PAGE_FLIP_ASYNC | \
> DRM_MODE_PAGE_FLIP_TARGET)
>
All of this uses DRM_MODE_LUT namespace but it seems specifically for
the drm colorop of type DRM_COLOROP_1D_LUT. Let's be consistent with the
naming.
> +/**
> + * DRM_MODE_LUT_INTERPOLATE
> + *
> + * linearly interpolate between the points
> + */
> +#define DRM_MODE_LUT_INTERPOLATE BIT(0)
> +
> +/**
> + * DRM_MODE_LUT_REUSE_LAST
> + *
> + * the last value of the previous range is the
> + * first value of the current range.
> + */
> +#define DRM_MODE_LUT_REUSE_LAST BIT(1)
> +
> +/**
> + * DRM_MODE_LUT_NON_DECREASING
> + *
> + * the curve must be non-decreasing
> + */
> +#define DRM_MODE_LUT_NON_DECREASING BIT(2)
> +
> +/**
> + * DRM_MODE_LUT_REFLECT_NEGATIVE
> + *
> + * the curve is reflected across origin for negative inputs
> + */
> +#define DRM_MODE_LUT_REFLECT_NEGATIVE BIT(3)
> +
> +/**
> + * DRM_MODE_LUT_SINGLE_CHANNEL
> + *
> + * the same curve (red) is used for blue and green channels as well
> + */
> +#define DRM_MODE_LUT_SINGLE_CHANNEL BIT(4)
> +
> +/**
> + * struct drm_color_lut_range
> + *
> + * structure to advertise capability of a color hardware
> + * block that accepts LUT values. It can represent LUTs with
> + * varied number of entries and distributions
> + * (Multi segmented, Logarithmic etc).
> + */
> +
> +struct drm_color_lut_range {
> + /* DRM_MODE_LUT_* */
> + __u32 flags;
> + /* number of points on the curve */
> + __u16 count;
> + /* input/output bits per component */
> + __u8 input_bpc, output_bpc;
> + /* input start/end values */
> + __s32 start, end;
> + /* output min/max values */
> + __s32 min, max;
> +};
> +
> /*
> * Request a page flip on the specified crtc.
> *
> --
> 2.42.0
>
next prev parent reply other threads:[~2024-02-13 12:04 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-13 6:48 [PATCH 00/28] Plane Color Pipeline support for Intel platforms Uma Shankar
2024-02-13 6:48 ` [PATCH 01/28] [NOT FOR REVIEW] drm: color pipeline base work Uma Shankar
2024-02-13 21:15 ` kernel test robot
2024-02-14 2:46 ` kernel test robot
2024-02-16 12:07 ` kernel test robot
2024-02-17 16:56 ` kernel test robot
2024-02-13 6:48 ` [PATCH 02/28] drm: Add missing function declarations Uma Shankar
2024-02-13 6:48 ` [PATCH 03/28] drm: handle NULL next colorop in drm_colorop_set_next_property Uma Shankar
2024-02-13 6:48 ` [PATCH 04/28] drm: Fix error logging in set Color Pipeline Uma Shankar
2024-02-13 6:48 ` [PATCH 05/28] drm: Add support for 3x3 CTM Uma Shankar
2024-02-13 9:15 ` Pekka Paalanen
2024-02-14 6:55 ` Shankar, Uma
2024-02-13 6:48 ` [PATCH 06/28] drm: Add Enhanced LUT precision structure Uma Shankar
2024-02-13 6:48 ` [PATCH 07/28] drm: Add 1D LUT color op Uma Shankar
2024-02-13 6:48 ` [PATCH 08/28] drm: Add Color lut range attributes Uma Shankar
2024-02-13 12:04 ` Sebastian Wick [this message]
2024-02-14 7:34 ` Shankar, Uma
2024-02-13 6:48 ` [PATCH 09/28] drm: Add Color ops capability property Uma Shankar
2024-02-13 12:04 ` Sebastian Wick
2024-02-14 7:36 ` Shankar, Uma
2024-02-13 6:48 ` [PATCH 10/28] drm: Define helper to create color " Uma Shankar
2024-02-13 6:48 ` [PATCH 11/28] drm: Define helper for adding capability property for 1D LUT Uma Shankar
2024-02-13 6:48 ` [PATCH 12/28] drm/i915: Add identifiers for intel color blocks Uma Shankar
2024-02-13 6:48 ` [PATCH 13/28] drm/i915: Add intel_color_op Uma Shankar
2024-02-13 6:48 ` [PATCH 14/28] drm/i915/color: Add helper to allocate intel colorop Uma Shankar
2024-02-13 6:48 ` [PATCH 15/28] drm/i915/color: Add helper to create " Uma Shankar
2024-02-13 6:48 ` [PATCH 16/28] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2024-02-19 7:34 ` Dan Carpenter
2024-02-13 6:48 ` [PATCH 17/28] drm/i915: Define segmented Lut and add capabilities to colorop Uma Shankar
2024-02-13 9:37 ` Pekka Paalanen
2024-02-14 7:28 ` Shankar, Uma
2024-02-14 9:03 ` Pekka Paalanen
2024-02-19 10:34 ` Shankar, Uma
2024-02-19 12:02 ` Pekka Paalanen
2024-02-13 6:48 ` [PATCH 18/28] drm/i915/color: Add and attach COLORPIPELINE plane property Uma Shankar
2024-02-13 6:48 ` [PATCH 19/28] drm/i915/color: Add framework to set colorop Uma Shankar
2024-02-13 6:48 ` [PATCH 20/28] drm/i915/color: Add callbacks to set plane CTM Uma Shankar
2024-02-13 6:48 ` [PATCH 21/28] drm/i915/color: Add plane CTM callback for TGL and beyond Uma Shankar
2024-02-13 6:48 ` [PATCH 22/28] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2024-02-13 6:48 ` [PATCH 23/28] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2024-02-13 6:48 ` [PATCH 24/28] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2024-02-13 6:48 ` [PATCH 25/28] drm/i915/color: Program Pre-CSC registers Uma Shankar
2024-02-13 6:48 ` [PATCH 26/28] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2024-02-13 6:48 ` [PATCH 27/28] FIXME: force disable legacy plane color properties for TGL and beyond Uma Shankar
2024-02-13 6:48 ` [PATCH 28/28] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2024-02-13 8:09 ` ✗ Fi.CI.CHECKPATCH: warning for Plane Color Pipeline support for Intel platforms Patchwork
2024-02-13 8:10 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-02-13 8:28 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-02-13 11:01 ` [PATCH 00/28] " Pekka Paalanen
2024-02-14 7:33 ` Shankar, Uma
2024-02-16 21:47 ` Harry Wentland
2024-02-19 10:49 ` Shankar, Uma
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