From: Clint Taylor <clinton.a.taylor@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: [PATCH v4 05/11] drm/i915/cx0: Extend C10 check to PTL
Date: Thu, 24 Oct 2024 15:31:08 -0700 [thread overview]
Message-ID: <20241024223114.785209-6-clinton.a.taylor@intel.com> (raw)
In-Reply-To: <20241024223114.785209-1-clinton.a.taylor@intel.com>
From: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
When deciding the type of the phy, add PTL support to make
sure the correct path is taken for selection of C10 PHY.
Only port A is connected C10 PHY for Pantherlake.
Bspec: 72571
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 +++
| 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index d05daa7a2b03..4d6e1c135bdc 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -34,6 +34,9 @@ bool intel_encoder_is_c10phy(struct intel_encoder *encoder)
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
enum phy phy = intel_encoder_to_phy(encoder);
+ if (IS_PANTHERLAKE(i915) && phy == PHY_A)
+ return true;
+
if ((IS_LUNARLAKE(i915) || IS_METEORLAKE(i915)) && phy < PHY_C)
return true;
--git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
index b7041b578e5e..bd8c3de57dcd 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h
@@ -67,6 +67,7 @@ static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
#define IS_METEORLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_METEORLAKE)
#define IS_LUNARLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_LUNARLAKE)
#define IS_BATTLEMAGE(dev_priv) IS_PLATFORM(dev_priv, XE_BATTLEMAGE)
+#define IS_PANTHERLAKE(dev_priv) IS_PLATFORM(dev_priv, XE_PANTHERLAKE)
#define IS_HASWELL_ULT(dev_priv) (dev_priv && 0)
#define IS_BROADWELL_ULT(dev_priv) (dev_priv && 0)
--
2.25.1
next prev parent reply other threads:[~2024-10-24 22:31 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-24 22:31 [PATCH v4 00/11] drm/i915/xe3lpd: ptl display patches Clint Taylor
2024-10-24 22:31 ` [PATCH v4 01/11] drm/i915/xe3lpd: Update pmdemand programming Clint Taylor
2024-10-25 13:31 ` Gustavo Sousa
2024-10-25 14:16 ` Jani Nikula
2024-10-24 22:31 ` [PATCH v4 02/11] drm/i915/xe3lpd: Disable HDCP Line Rekeying for Xe3 Clint Taylor
2024-10-24 22:31 ` [PATCH v4 03/11] drm/i915/xe3lpd: Add check to see if edp over type c is allowed Clint Taylor
2024-10-25 5:00 ` Murthy, Arun R
2024-10-25 15:29 ` Jani Nikula
2024-10-24 22:31 ` [PATCH v4 04/11] drm/i915/ptl: Define IS_PANTHERLAKE macro Clint Taylor
2024-10-24 22:31 ` Clint Taylor [this message]
2024-10-24 22:31 ` [PATCH v4 06/11] drm/i915/cx0: Remove bus reset after every c10 transaction Clint Taylor
2024-10-25 13:52 ` Gustavo Sousa
2024-10-24 22:31 ` [PATCH v4 07/11] drm/i915/xe3lpd: Move async flip bit to PLANE_SURF register Clint Taylor
2024-10-24 22:31 ` [PATCH v4 08/11] drm/i915/xe3: Underrun recovery does not exist post Xe2 Clint Taylor
2024-10-24 22:31 ` [PATCH v4 09/11] drm/i915/display/xe3: disable x-tiled framebuffers Clint Taylor
2024-10-24 22:31 ` [PATCH v4 10/11] drm/i915/xe3lpd: Skip disabling VRR during modeset disable Clint Taylor
2024-10-25 8:06 ` Golani, Mitulkumar Ajitkumar
2024-10-25 10:18 ` Golani, Mitulkumar Ajitkumar
2024-10-24 22:31 ` [PATCH v4 11/11] drm/i915/xe3lpd: Power request asserting/deasserting Clint Taylor
2024-10-25 13:58 ` Gustavo Sousa
2024-10-24 23:11 ` ✗ Fi.CI.SPARSE: warning for drm/i915/xe3lpd: ptl display patches (rev4) Patchwork
2024-10-24 23:39 ` ✓ Fi.CI.BAT: success " Patchwork
2024-10-25 1:34 ` ✗ Fi.CI.IGT: failure " Patchwork
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