From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
Subject: [PATCH 11/16] drm/i915/vblank: Add helper to get correct vblank length
Date: Mon, 6 Oct 2025 09:58:47 +0530 [thread overview]
Message-ID: <20251006042852.263249-12-ankit.k.nautiyal@intel.com> (raw)
In-Reply-To: <20251006042852.263249-1-ankit.k.nautiyal@intel.com>
Currently crtc_vblank_start is assumed to be the vblank_start for the fixed
refresh rate case. That value can be different from the variable refresh
rate case whenever always_use_vrr_tg()==false. On icl/tgl it's always
different due to the extra vblank delay, and also on adl+ it could be
different if we were to use an optimized guardband.
So places where crtc_vblank_start is used to compute vblank length needs
change so as to account for cases where vrr is enabled. Specifically
with vrr.enable the effective vblank length is actually guardband.
Add a helper to get the correct vblank length for both vrr and fixed
refresh rate cases. Use this helper where vblank_start is used to
compute the vblank length.
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
drivers/gpu/drm/i915/display/intel_pfit.c | 11 +++++++----
drivers/gpu/drm/i915/display/intel_psr.c | 3 +--
drivers/gpu/drm/i915/display/intel_vblank.c | 10 ++++++++++
drivers/gpu/drm/i915/display/intel_vblank.h | 2 ++
drivers/gpu/drm/i915/display/skl_watermark.c | 3 ++-
5 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_pfit.c b/drivers/gpu/drm/i915/display/intel_pfit.c
index 68539e7c2a24..ebbaa1d419ba 100644
--- a/drivers/gpu/drm/i915/display/intel_pfit.c
+++ b/drivers/gpu/drm/i915/display/intel_pfit.c
@@ -14,6 +14,7 @@
#include "intel_lvds_regs.h"
#include "intel_pfit.h"
#include "intel_pfit_regs.h"
+#include "intel_vblank.h"
#include "skl_scaler.h"
static int intel_pch_pfit_check_dst_window(const struct intel_crtc_state *crtc_state)
@@ -306,14 +307,15 @@ centre_horizontally(struct drm_display_mode *adjusted_mode,
}
static void
-centre_vertically(struct drm_display_mode *adjusted_mode,
+centre_vertically(struct intel_crtc_state *crtc_state,
+ struct drm_display_mode *adjusted_mode,
int height)
{
u32 border, sync_pos, blank_width, sync_width;
/* keep the vsync and vblank widths constant */
sync_width = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
- blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start;
+ blank_width = intel_crtc_vblank_length(crtc_state);
sync_pos = (blank_width - sync_width + 1) / 2;
border = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
@@ -392,7 +394,8 @@ static void i9xx_scale_aspect(struct intel_crtc_state *crtc_state,
PFIT_HORIZ_INTERP_BILINEAR);
}
} else if (scaled_width < scaled_height) { /* letter */
- centre_vertically(adjusted_mode,
+ centre_vertically(crtc_state,
+ adjusted_mode,
scaled_width / pipe_src_w);
*border = LVDS_BORDER_ENABLE;
@@ -489,7 +492,7 @@ static int gmch_panel_fitting(struct intel_crtc_state *crtc_state,
* heights and modify the values programmed into the CRTC.
*/
centre_horizontally(adjusted_mode, pipe_src_w);
- centre_vertically(adjusted_mode, pipe_src_h);
+ centre_vertically(crtc_state, adjusted_mode, pipe_src_h);
border = LVDS_BORDER_ENABLE;
break;
case DRM_MODE_SCALE_ASPECT:
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index f7115969b4c5..ae6b94a5d450 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1365,8 +1365,7 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp,
bool aux_less)
{
struct intel_display *display = to_intel_display(intel_dp);
- int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end -
- crtc_state->hw.adjusted_mode.crtc_vblank_start;
+ int vblank = intel_crtc_vblank_length(crtc_state);
int wake_lines;
if (aux_less)
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 0b7fcc05e64c..2fc0c1c0bb87 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -767,3 +767,13 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
return scanline;
}
+
+int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state)
+{
+ const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
+
+ if (crtc_state->vrr.enable)
+ return crtc_state->vrr.guardband;
+ else
+ return adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
index 21fbb08d61d5..98d04cacd65f 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.h
+++ b/drivers/gpu/drm/i915/display/intel_vblank.h
@@ -48,4 +48,6 @@ const struct intel_crtc_state *
intel_pre_commit_crtc_state(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+int intel_crtc_vblank_length(const struct intel_crtc_state *crtc_state);
+
#endif /* __INTEL_VBLANK_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 73e5b2d8ae83..6fb2c78fe29b 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -28,6 +28,7 @@
#include "intel_flipq.h"
#include "intel_pcode.h"
#include "intel_plane.h"
+#include "intel_vblank.h"
#include "intel_wm.h"
#include "skl_universal_plane_regs.h"
#include "skl_scaler.h"
@@ -2171,7 +2172,7 @@ skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state,
return crtc_state->framestart_delay +
intel_usecs_to_scanlines(adjusted_mode, latency) +
wm0_lines >
- adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vblank_start;
+ intel_crtc_vblank_length(crtc_state);
}
int skl_max_wm0_lines(const struct intel_crtc_state *crtc_state)
--
2.45.2
next prev parent reply other threads:[~2025-10-06 4:42 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-06 4:28 [PATCH 00/16] Optimize vrr.guardband and fix LRR Ankit Nautiyal
2025-10-06 4:28 ` [PATCH 01/16] drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/end Ankit Nautiyal
2025-10-06 4:28 ` [PATCH 02/16] drm/i915/skl_watermark: Fix the scaling factor for chroma subsampling Ankit Nautiyal
2025-10-06 4:28 ` [PATCH 03/16] drm/i915/skl_watermark: Pass linetime as argument to latency helpers Ankit Nautiyal
2025-10-06 4:28 ` [PATCH 04/16] drm/i915/skl_scaler: Introduce helper for chroma downscale factor Ankit Nautiyal
2025-10-06 4:28 ` [PATCH 05/16] drm/i915/display: Extract helpers to set dsc/scaler prefill latencies Ankit Nautiyal
2025-10-06 4:28 ` [PATCH 06/16] drm/i915/dp: Add SDP latency computation helper Ankit Nautiyal
2025-10-06 4:28 ` [PATCH 07/16] drm/i915/alpm: Add function to compute max link-wake latency Ankit Nautiyal
2025-10-06 4:28 ` [PATCH 08/16] drm/i915/display: Add guardband check for feature latencies Ankit Nautiyal
2025-10-06 4:28 ` [PATCH 09/16] drm/i915/skl_watermark: Remove redundant latency checks from vblank validation Ankit Nautiyal
2025-10-06 4:28 ` [PATCH 10/16] drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband Ankit Nautiyal
2025-10-06 4:28 ` Ankit Nautiyal [this message]
2025-10-06 19:56 ` [PATCH 11/16] drm/i915/vblank: Add helper to get correct vblank length Ville Syrjälä
2025-10-07 5:52 ` Nautiyal, Ankit K
2025-10-07 15:16 ` Ville Syrjälä
2025-10-07 17:30 ` Ville Syrjälä
2025-10-08 6:34 ` Nautiyal, Ankit K
2025-10-06 4:28 ` [PATCH 12/16] drm/i915/vrr: Recompute vblank_start for platforms with always-on VRR TG Ankit Nautiyal
2025-10-06 4:28 ` [PATCH 13/16] drm/i915/display: Add vblank_start adjustment logic for " Ankit Nautiyal
2025-10-06 19:56 ` Ville Syrjälä
2025-10-07 6:30 ` Nautiyal, Ankit K
2025-10-07 15:19 ` Ville Syrjälä
2025-10-06 4:28 ` [PATCH 14/16] drm/i915/vrr: Introduce helper to compute min static guardband Ankit Nautiyal
2025-10-06 4:28 ` [PATCH 15/16] drm/i915/display: Use optimized guardband for always-on VRR TG Ankit Nautiyal
2025-10-06 4:28 ` [PATCH 16/16] drm/i915/vrr: Use optimized guardband when VRR TG is active Ankit Nautiyal
2025-10-06 9:56 ` ✓ i915.CI.BAT: success for Optimize vrr.guardband and fix LRR (rev13) Patchwork
2025-10-06 11:54 ` ✗ i915.CI.Full: failure " Patchwork
2025-10-06 22:50 ` [PATCH 00/16] Optimize vrr.guardband and fix LRR Ville Syrjälä
2025-10-07 6:33 ` Nautiyal, Ankit K
2025-10-07 15:22 ` Ville Syrjälä
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