From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 2/3] drm/i915/dram: Sort SKL+ DIMM register bits
Date: Wed, 29 Oct 2025 22:42:14 +0200 [thread overview]
Message-ID: <20251029204215.12292-3-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20251029204215.12292-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use the customary big endian order when defining the
SKL/ICL DIMM registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_mchbar_regs.h | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_mchbar_regs.h b/drivers/gpu/drm/i915/intel_mchbar_regs.h
index 378dc7c69f7d..a46a45b9d2e1 100644
--- a/drivers/gpu/drm/i915/intel_mchbar_regs.h
+++ b/drivers/gpu/drm/i915/intel_mchbar_regs.h
@@ -161,24 +161,24 @@
#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
#define SKL_DRAM_S_SHIFT 16
-#define SKL_DRAM_SIZE_MASK REG_GENMASK(5, 0)
+#define SKL_DRAM_RANK_MASK REG_GENMASK(10, 10)
+#define SKL_DRAM_RANK_1 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 0)
+#define SKL_DRAM_RANK_2 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 1)
#define SKL_DRAM_WIDTH_MASK REG_GENMASK(9, 8)
#define SKL_DRAM_WIDTH_X8 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 0)
#define SKL_DRAM_WIDTH_X16 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 1)
#define SKL_DRAM_WIDTH_X32 REG_FIELD_PREP(SKL_DRAM_WIDTH_MASK, 2)
-#define SKL_DRAM_RANK_MASK REG_GENMASK(10, 10)
-#define SKL_DRAM_RANK_1 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 0)
-#define SKL_DRAM_RANK_2 REG_FIELD_PREP(SKL_DRAM_RANK_MASK, 1)
-#define ICL_DRAM_SIZE_MASK REG_GENMASK(6, 0)
-#define ICL_DRAM_WIDTH_MASK REG_GENMASK(8, 7)
-#define ICL_DRAM_WIDTH_X8 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 0)
-#define ICL_DRAM_WIDTH_X16 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 1)
-#define ICL_DRAM_WIDTH_X32 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 2)
+#define SKL_DRAM_SIZE_MASK REG_GENMASK(5, 0)
#define ICL_DRAM_RANK_MASK REG_GENMASK(10, 9)
#define ICL_DRAM_RANK_1 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 0)
#define ICL_DRAM_RANK_2 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 1)
#define ICL_DRAM_RANK_3 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 2)
#define ICL_DRAM_RANK_4 REG_FIELD_PREP(ICL_DRAM_RANK_MASK, 3)
+#define ICL_DRAM_WIDTH_MASK REG_GENMASK(8, 7)
+#define ICL_DRAM_WIDTH_X8 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 0)
+#define ICL_DRAM_WIDTH_X16 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 1)
+#define ICL_DRAM_WIDTH_X32 REG_FIELD_PREP(ICL_DRAM_WIDTH_MASK, 2)
+#define ICL_DRAM_SIZE_MASK REG_GENMASK(6, 0)
#define SA_PERF_STATUS_0_0_0_MCHBAR_PC _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5918)
#define DG1_QCLK_RATIO_MASK REG_GENMASK(9, 2)
--
2.49.1
next prev parent reply other threads:[~2025-10-29 20:42 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-29 20:42 [PATCH 0/3] drm/1915/dram: Fix DIMM_S decoding on ICL Ville Syrjala
2025-10-29 20:42 ` [PATCH 1/3] drm/i915/dram: Use REG_GENMASK() & co. for the SKL+ DIMM regs Ville Syrjala
2025-11-05 20:45 ` Lucas De Marchi
2025-10-29 20:42 ` Ville Syrjala [this message]
2025-11-05 20:48 ` [PATCH 2/3] drm/i915/dram: Sort SKL+ DIMM register bits Lucas De Marchi
2025-10-29 20:42 ` [PATCH 3/3] drm/i915/dram: Fix ICL DIMM_S decoding Ville Syrjala
2025-11-05 22:25 ` Lucas De Marchi
2025-11-07 13:37 ` Ville Syrjälä
2025-11-19 8:05 ` Jani Nikula
2025-10-30 22:43 ` ✓ i915.CI.BAT: success for drm/1915/dram: Fix DIMM_S decoding on ICL Patchwork
2025-10-31 11:53 ` ✓ i915.CI.Full: " Patchwork
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