[RFC 0/7] drm/display/dp_tunnel: Add debugfs surface for BWA validation

[Kunal Joshi <kunal1.joshi@intel.com>]

Add a debugfs surface to the DRM display DP-tunnel core so IGT
(kms_tbt) can drive deterministic tests of Bandwidth Allocation
Mode on Thunderbolt / USB4 docks without depending on transient
sink behaviour.

Three debugfs files are exposed per tunnel:
  - info       (read-only)  estimated BW, allocated BW, DPRX caps, BWA state
  - bw_alloc_enable (r/w)   toggle BWA on/off
  - bw_limit        (r/w)   inject a BW cap for mode-filtering pressure

Patches 1-3 add the DRM-core helpers, 4-5 wire them into i915,
and 6-7 fix two latent BWA bugs found while testing:
  - allocated_bw not synced after BWA enable (teardown loop)
  - MST children lose dp_tunnel/ after tunnel re-detect

Companion IGT series (kms_tbt) posted separately.

Kunal Joshi (7):
  drm/display/dp_tunnel: Add debugfs interface with info file
  drm/display/dp_tunnel: Add bw_alloc_enable debugfs knob
  drm/display/dp_tunnel: Add bw_limit debugfs cap for BW pressure
    injection
  drm/i915/dp_tunnel: Wire up DP tunnel debugfs from DRM core
  drm/i915/display: Expose DP tunnel debugfs under each connector
  drm/display/dp_tunnel: Sync SW allocated_bw after enabling BW alloc
  drm/i915/dp_tunnel: Re-attach dp_tunnel debugfs to MST children on
    re-detect

 drivers/gpu/drm/display/drm_dp_tunnel.c       | 402 +++++++++++++++++-
 .../drm/i915/display/intel_display_debugfs.c  |  22 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  11 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   |  11 +
 .../gpu/drm/i915/display/intel_dp_tunnel.c    |  50 ++-
 include/drm/display/drm_dp_tunnel.h           |  17 +
 6 files changed, 511 insertions(+), 2 deletions(-)

-- 
2.25.1