From: Uma Shankar <uma.shankar@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: vinod.govindapillai@intel.com, suraj.kandpal@intel.com,
Uma Shankar <uma.shankar@intel.com>
Subject: [v3 0/2] drm/i915/display: Implement Display Wa_16030862157
Date: Wed, 15 Jul 2026 20:02:41 +0530 [thread overview]
Message-ID: <20260715143243.4141208-1-uma.shankar@intel.com> (raw)
Interpret 0xF populated-channel count as 16. For 16-channel
configuration, BIOS programs 1111b. A programmed value of 1111b
must be interpreted as 16 channels for memory bandwidth calculations.
This series implements the workaround in driver.
v2:
- Logical separation of changes
- Limit WA to NVL
Uma Shankar (2):
drm/i915/xe3p/dram: Interpret 0xF populated-channel count as 16
drm/i915/xe3p/bw: Update bw calculation to account for 16 channels
drivers/gpu/drm/i915/display/intel_bw.c | 20 ++++++++++++++++---
.../gpu/drm/i915/display/intel_display_wa.c | 2 ++
.../gpu/drm/i915/display/intel_display_wa.h | 1 +
drivers/gpu/drm/i915/display/intel_dram.c | 14 ++++++++++++-
4 files changed, 33 insertions(+), 4 deletions(-)
--
2.50.1
next reply other threads:[~2026-07-15 14:13 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-15 14:32 Uma Shankar [this message]
2026-07-15 14:32 ` [v3 1/2] drm/i915/xe3p/dram: Interpret 0xF populated-channel count as 16 Uma Shankar
2026-07-16 2:40 ` Kandpal, Suraj
2026-07-16 9:47 ` Govindapillai, Vinod
2026-07-15 14:32 ` [v3 2/2] drm/i915/xe3p/bw: Update bw calculation to account for 16 channels Uma Shankar
2026-07-16 2:41 ` Kandpal, Suraj
2026-07-16 9:49 ` Govindapillai, Vinod
2026-07-15 16:42 ` ✓ i915.CI.BAT: success for drm/i915/display: Implement Display Wa_16030862157 (rev2) Patchwork
2026-07-15 21:59 ` ✗ i915.CI.Full: failure " Patchwork
2026-07-17 15:47 ` ✓ i915.CI.Full: success " Patchwork
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