From: sashiko-bot@kernel.org
To: "Ville Syrjala" <ville.syrjala@linux.intel.com>
Cc: intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 04/14] drm/i915/cdclk: Notify DG2 pcode about pipe power wells regardless of CDCLK
Date: Wed, 26 Aug 2026 13:58:13 +0000 [thread overview]
Message-ID: <20260826135814.296981F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260826134033.13976-5-ville.syrjala@linux.intel.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [High] The function `dg2_power_well_count` incorrectly returns a `bool` instead of an integer type, causing the active pipe count to be silently truncated to 1 for any multi-pipe configuration. This breaks the new equality checks introduced in this patch, preventing PCODE notifications during multi-pipe display transitions.
--
commit fcc366768f01016ec317b427777b27612fa4fe66
Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
drm/i915/cdclk: Notify DG2 pcode about pipe power wells regardless of CDCLK
This patch updates the early return logic in CDCLK pre/post plane update
functions. It ensures DG2 pcode notifications are sent when pipe power well
counts change, even if the actual CDCLK remains unchanged.
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index d96067d7346b7..570c257626066 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2841,7 +2841,9 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
> return;
>
> if (!intel_cdclk_changed(&old_cdclk_state->actual,
> - &new_cdclk_state->actual))
> + &new_cdclk_state->actual) &&
> + dg2_power_well_count(display, old_cdclk_state) ==
> + dg2_power_well_count(display, new_cdclk_state))
[Severity: High]
This isn't a bug introduced by this patch, but does this new equality check
work correctly given the return type of dg2_power_well_count()?
Looking at dg2_power_well_count() in intel_cdclk.c:
static bool dg2_power_well_count(struct intel_display *display,
const struct intel_cdclk_state *cdclk_state)
{
return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0;
}
Because it returns a bool instead of an integer type, any non-zero pipe count
returned by hweight8() will be truncated to 1 (true).
If a user transitions between non-zero active pipe counts (for example, going
from 1 to 2 pipes during a hotplug), the check will evaluate to true == true.
Could this falsely trigger the early return and skip the required pcode
notification on DG2?
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260826134033.13976-1-ville.syrjala@linux.intel.com?part=4
next prev parent reply other threads:[~2026-08-26 13:58 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-26 13:40 [PATCH v2 00/14] drm/i915/cdclk: cdclk pcode related fixes and refactoring Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 01/14] drm/i915/cdclk: Don't bail if pcode post nofify fails Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 02/14] drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2 Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 03/14] drm/i915/cdclk: Do the DG2 CDCLK/pipe power well notify properly Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 04/14] drm/i915/cdclk: Notify DG2 pcode about pipe power wells regardless of CDCLK Ville Syrjala
2026-08-26 13:58 ` sashiko-bot [this message]
2026-08-26 13:40 ` [PATCH v2 05/14] drm/i915/cdclk: Stop forcing voltage level to 3 all the time on DG2 Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 06/14] drm/i915/cdclk: Drop pointless platform check from bxt_set_cdclk() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 07/14] drm/i915/dg2: s/intel_/dg2_/ for DG2 specific stuff Ville Syrjala
2026-08-26 13:52 ` sashiko-bot
2026-08-26 13:40 ` [PATCH v2 08/14] drm/i915/cdclk: Unify the pcode pre/post notify in bxt_set_cdclk() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 09/14] drm/i915/cdclk: Unify pcode related debugs Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 10/14] drm/i915/cdclk: Extract bdw_cdclk_pcode_{pre, post}_notify() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 11/14] drm/i915/cdclk: Extract skl_cdclk_pcode_{pre, post}_notify() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 12/14] drm/i915/cdclk: Extract bxt_cdclk_pcode_{pre, post}_notify() Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 13/14] drm/i915/cdclk: Introduce CDCLK .{pre, post}_notify() vfuncs Ville Syrjala
2026-08-26 13:40 ` [PATCH v2 14/14] drm/i915/cdclk: Hoist intel_cdclk_{pre, post}_notify() calls upwards Ville Syrjala
2026-08-26 15:28 ` ✓ i915.CI.BAT: success for drm/i915/cdclk: cdclk pcode related fixes and refactoring (rev2) Patchwork
2026-08-26 20:53 ` ✗ i915.CI.Full: failure " Patchwork
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