Re: [PATCH] drm/i915/dp: fix PBN in ALLOCATE_PAYLOAD request to use actual video bandwidth

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] drm/i915: decoupling MST time slots from aligned TU size breaks VCPI allocation
--

commit d39c8c4fc3f7e04d619491dd803df11282c8c97a
Author: Xiao Lu <xiaolu.xie@intel.com>
Subject: drm/i915/dp: fix PBN in ALLOCATE_PAYLOAD request to use actual video bandwidth

This commit fixes an issue where the TU-aligned PBN value was being passed
to drm_dp_atomic_find_time_slots(), causing the MST core's bandwidth check
to fail for configurations that should fit. It separates the raw PBN from
the TU-aligned PBN, passing raw_pbn for payload allocation while retaining
the aligned PBN for TU hardware programming.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
[ ... ]
> @@ -397,7 +398,21 @@ int intel_dp_mtp_tu_compute_config(struct intel_dp *intel_dp,
>  
>  			slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst.mgr,
>  							      connector->mst.port,
> -							      dfixed_trunc(pbn));
> +							      raw_pbn);

[Severity: High]
Does passing the unaligned raw_pbn cause the MST core to allocate an
unaligned number of time slots? This seems to decouple the MST core's VCPI
allocation from the driver's aligned hardware TU size in
intel_dp_mtp_tu_compute_config(), which can corrupt the MTP payload framing
and overrun the MTP total slot capacity.

> +
> +			drm_dbg_kms(display->drm,
> +				    "MST TU %s pipe %c: clock=%d lanes=%d bpp=%d link_bpp=%d fec=%d\n",
> +				    connector->base.name,
> +				    pipe_name(to_intel_crtc(crtc_state->uapi.crtc)->pipe),
> +				    crtc_state->port_clock, crtc_state->lane_count,
> +				    fxp_q4_to_int(bpp_x16), fxp_q4_to_int(link_bpp_x16),
> +				    crtc_state->fec_enable);
> +			drm_dbg_kms(display->drm,
> +				    "MST TU %s: overhead=%d raw_pbn=%d pbn=%d pbn_div=%d tu=%d slots=%d full_pbn=%d\n",
> +				    connector->base.name,
> +				    remote_bw_overhead, raw_pbn,
> +				    dfixed_trunc(pbn), dfixed_trunc(mst_state->pbn_div),
> +				    remote_tu, slots, connector->mst.port->full_pbn);
>  
>  			/* TODO: Check this already in drm_dp_atomic_find_time_slots(). */
>  			if (slots > mst_state->total_avail_slots)
>  				slots = -EINVAL;

[Severity: High]
This capacity check now only validates the unaligned count. Could this allow
configurations where the aligned hardware TU size exceeds the available MTP
slots to pass the check?

[ ... ]
> 		if (slots == -EDEADLK)
> 			return slots;
> 
> 		if (slots >= 0) {
> 			drm_WARN_ON(display->drm, slots != crtc_state->dp_m_n.tu);

[Severity: High]
Will this assertion trigger consistently now? Because slots (unaligned) will
no longer match crtc_state->dp_m_n.tu (which is aligned), this might cause
persistent kernel WARN_ON stack traces (crashing systems with panic_on_warn)
on DP MST modesets where the raw video bandwidth results in an unaligned TU
count.

> 
> 			break;
> 		}

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260922081258.1995510-1-xiaolu.xie@intel.com?part=1