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From: Danylo Dobushovkyi <dobushovsky@gmail.com>
To: intel-gfx@lists.freedesktop.org
Cc: arun.r.murthy@intel.com, jani.nikula@linux.intel.com,
	Danylo Dobushovkyi <dobushovsky@gmail.com>
Subject: [PATCH v3] drm/i915/pps: reconcile a BIOS-enabled VDD without leaking its wakeref
Date: Sat,  3 Oct 2026 23:41:57 +0300	[thread overview]
Message-ID: <20261003204157.6107-1-dobushovsky@gmail.com> (raw)
In-Reply-To: <20260831093854.1427305-1-arun.r.murthy@intel.com>

When the BIOS leaves the eDP VDD force bit (EDP_FORCE_VDD) enabled at boot,
the driver adopts that state by taking an AUX power-domain reference into
intel_dp->pps.vdd_wakeref.

In v2 of this patch, an attempt was made to track this handover via a
vdd_wakeref_boot flag. However, it missed the delayed VDD off-path. If the
hardware VDD bit is cleared asynchronously (by BIOS, DMC, or DC states),
intel_pps_vdd_off_sync_unlocked() returns early because edp_have_panel_vdd()
is false, stranding the wakeref. Later, when the panel is turned on again,
the on-path overwrites the dangling pointer, permanently leaking the wakeref
(i915 raw-wakerefs=1 wakelocks=1 on cleanup).

This v3 patch fixes the leak completely by:
1. Preventing the early return in the off-path if we still hold a software
   wakeref, ensuring it is properly released regardless of HW state.
2. Using the boot flag to reuse the reference on the first boot handover.
3. Adding a strict check in the on-path to NEVER overwrite an existing
   wakeref if a logical imbalance occurs, while preserving the WARN_ON
   to catch state mismatches.

Tested on an HP Victus (s2idle).

Based on the original v2 idea by Arun R Murthy <arun.r.murthy@intel.com>.

Signed-off-by: Danylo Dobushovkyi <dobushovsky@gmail.com>
---
 .../gpu/drm/i915/display/intel_display_types.h  |  4 ++++
 drivers/gpu/drm/i915/display/intel_pps.c        | 17 +++++++++++++----
 2 files changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9642264..ea46c13 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1709,6 +1709,10 @@ struct intel_pps {
 	unsigned long last_backlight_off;
 	ktime_t panel_power_off_time;
 	struct ref_tracker *vdd_wakeref;
+	/* vdd_wakeref was adopted from an already-on VDD at the BIOS/firmware
+	 * handover (boot/resume) and not yet reconciled into normal ownership.
+	 */
+	bool vdd_wakeref_boot;
 
 	union {
 		/*
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index d4c98b1..38e7a34 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -758,9 +758,15 @@ bool intel_pps_vdd_on_unlocked(struct intel_dp *intel_dp)
 	if (edp_have_panel_vdd(intel_dp))
 		return need_to_disable;
 
-	drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
-	intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
-							    intel_aux_power_domain(dig_port));
+	if (intel_dp->pps.vdd_wakeref_boot) {
+		intel_dp->pps.vdd_wakeref_boot = false;
+	} else {
+		drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
+		if (!intel_dp->pps.vdd_wakeref)
+			intel_dp->pps.vdd_wakeref =
+				intel_display_power_get(display,
+							intel_aux_power_domain(dig_port));
+	}
 
 	pp_stat_reg = _pp_stat_reg(intel_dp);
 	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
@@ -832,7 +838,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
 
 	drm_WARN_ON(display->drm, intel_dp->pps.want_panel_vdd);
 
-	if (!edp_have_panel_vdd(intel_dp))
+	if (!edp_have_panel_vdd(intel_dp) && !intel_dp->pps.vdd_wakeref)
 		return;
 
 	drm_dbg_kms(display->drm, "[ENCODER:%d:%s] %s turning VDD off\n",
@@ -861,6 +867,7 @@ static void intel_pps_vdd_off_sync_unlocked(struct intel_dp *intel_dp)
 		intel_dp_invalidate_source_oui(intel_dp);
 	}
 
+	intel_dp->pps.vdd_wakeref_boot = false;
 	intel_display_power_put(display,
 				intel_aux_power_domain(dig_port),
 				fetch_and_zero(&intel_dp->pps.vdd_wakeref));
@@ -1063,6 +1070,7 @@ void intel_pps_off_unlocked(struct intel_dp *intel_dp)
 	intel_dp_invalidate_source_oui(intel_dp);
 
 	/* We got a reference when we enabled the VDD. */
+	intel_dp->pps.vdd_wakeref_boot = false;
 	intel_display_power_put(display,
 				intel_aux_power_domain(dig_port),
 				fetch_and_zero(&intel_dp->pps.vdd_wakeref));
@@ -1337,6 +1345,7 @@ static void pps_vdd_init(struct intel_dp *intel_dp)
 	drm_WARN_ON(display->drm, intel_dp->pps.vdd_wakeref);
 	intel_dp->pps.vdd_wakeref = intel_display_power_get(display,
 							    intel_aux_power_domain(dig_port));
+	intel_dp->pps.vdd_wakeref_boot = true;
 }
 
 bool intel_pps_have_panel_power_or_vdd(struct intel_dp *intel_dp)
-- 
2.56.0


  parent reply	other threads:[~2026-10-05 23:53 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-31  4:40 [PATCH] drm/i915/pps: don't orphan the VDD wakeref when the HW force bit is reset Arun R Murthy
2026-08-31  4:57 ` sashiko-bot
2026-08-31  5:22 ` ✓ i915.CI.BAT: success for " Patchwork
2026-08-31  6:32 ` [PATCH] " Jani Nikula
2026-09-02  8:52   ` Murthy, Arun R
2026-08-31  7:33 ` ✗ i915.CI.Full: failure for " Patchwork
2026-08-31  9:38 ` [PATCHv2] drm/i915/pps: reconcile a BIOS-enabled VDD without leaking its wakeref Arun R Murthy
2026-08-31  9:58   ` sashiko-bot
2026-10-03 20:41   ` Danylo Dobushovkyi [this message]
2026-08-31 15:26 ` ✓ i915.CI.BAT: success for drm/i915/pps: don't orphan the VDD wakeref when the HW force bit is reset (rev2) Patchwork
2026-08-31 21:21 ` ✓ i915.CI.Full: " Patchwork
2026-09-21 20:21 ` [PATCH] drm/i915/pps: don't orphan the VDD wakeref when the HW force bit is reset Claude Code (AI assistant, for an i915 user)

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