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From: "Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>
To: "Harrison, John C" <john.c.harrison@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Auld, Matthew" <matthew.auld@intel.com>,
	"Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>
Subject: Re: [Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
Date: Thu, 1 Sep 2022 15:49:50 +0000	[thread overview]
Message-ID: <2d7c041b6a7a5ef532703c802c31c0e91ae9a73e.camel@intel.com> (raw)
In-Reply-To: <DM8PR11MB57517286A18D8F58F8D330CC8A6C9@DM8PR11MB5751.namprd11.prod.outlook.com>

I think i found the problem - will trybot next before reposting a new rev.

was a terribly careless typo when rebasing from internal for drmtip:
guc_context_sched_disable called do_sched_disable which was supposed to call __guc_context_sched_disable (if the context
was really meant to be finally disabled) but instead called guc_context_sched_disable (no underscore) causing an
infinite loop for mid-disabling.

...alan

On Fri, 2022-08-19 at 16:47 +0000, Teres Alexis, Alan Previn wrote:
> Will look into this - apologies for the trouble Matt. 
> ...alan
> 
> -----Original Message-----
> From: Harrison, John C <john.c.harrison@intel.com> 
> Sent: Friday, August 19, 2022 8:46 AM
> To: Auld, Matthew <matthew.auld@intel.com>; intel-gfx@lists.freedesktop.org
> Cc: Brost, Matthew <matthew.brost@intel.com>; Teres Alexis, Alan Previn <alan.previn.teres.alexis@intel.com>
> Subject: Re: [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero"
> 
> On 8/19/2022 05:39, Matthew Auld wrote:
> > This reverts commit 6a079903847cce1dd06345127d2a32f26d2cd9c6.
> > 
> > Everything in CI using GuC is now timing out[1], and killing the 
> > machine with this change (perhaps a deadlock?). CI was recently on 
> > fire due to some changes coming in from -rc1, so likely the pre-merge 
> > CI results for this series were invalid? For now just revert, unless 
> > GuC experts already have a fix in mind.
> > 
> > [1] https://intel-gfx-ci.01.org/tree/drm-tip/index.html?
> > 
> > Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> > Cc: Matthew Brost <matthew.brost@intel.com>
> > Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> > Cc: John Harrison <John.C.Harrison@Intel.com>
> Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
> 
> Given that CI was claiming a pass for the original patch set, no we don't have a fix in mind. It is most frustrating when CI says all green if the entire universe is so broken that no tests were even running :(.
> 
> John.
> 
> 
> > ---
> >   drivers/gpu/drm/i915/gem/i915_gem_context.c   |   2 +-
> >   drivers/gpu/drm/i915/gt/intel_context.h       |   8 -
> >   drivers/gpu/drm/i915/gt/intel_context_types.h |   7 -
> >   drivers/gpu/drm/i915/gt/uc/intel_guc.h        |  17 +-
> >   .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c    |  60 -------
> >   .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 154 +++---------------
> >   drivers/gpu/drm/i915/i915_selftest.h          |   2 -
> >   7 files changed, 27 insertions(+), 223 deletions(-)
> > 

  reply	other threads:[~2022-09-01 15:50 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-19 12:39 [Intel-gfx] [PATCH] Revert "drm/i915/guc: Add delay to disable scheduling after pin count goes to zero" Matthew Auld
2022-08-19 13:25 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for " Patchwork
2022-08-19 13:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-08-19 15:46 ` [Intel-gfx] [PATCH] " John Harrison
2022-08-19 16:47   ` Teres Alexis, Alan Previn
2022-09-01 15:49     ` Teres Alexis, Alan Previn [this message]
2022-08-20 13:13 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork

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