From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Andi Shyti <andi.shyti@linux.intel.com>,
Intel GFX <intel-gfx@lists.freedesktop.org>,
DRI Devel <dri-devel@lists.freedesktop.org>
Cc: Matthew Auld <matthew.auld@intel.com>,
Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/gem: Flush TLBs for all the tiles
Date: Wed, 11 May 2022 08:23:04 +0100 [thread overview]
Message-ID: <2ecc20eb-a80c-8643-4cc8-8f9e18b5919d@linux.intel.com> (raw)
In-Reply-To: <20220510203359.92530-1-andi.shyti@linux.intel.com>
On 10/05/2022 21:33, Andi Shyti wrote:
> During object cleanup we invalidate the TLBs but we do it only
> for gt0. Invalidate the caches for all the tiles.
>
> Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_pages.c | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_pages.c b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> index 97c820eee115a..444b9f96ba77c 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_pages.c
> @@ -217,10 +217,15 @@ __i915_gem_object_unset_pages(struct drm_i915_gem_object *obj)
>
> if (test_and_clear_bit(I915_BO_WAS_BOUND_BIT, &obj->flags)) {
> struct drm_i915_private *i915 = to_i915(obj->base.dev);
> - intel_wakeref_t wakeref;
> + struct intel_gt *gt;
> + int i;
>
> - with_intel_runtime_pm_if_active(&i915->runtime_pm, wakeref)
> - intel_gt_invalidate_tlbs(to_gt(i915));
> + for_each_gt(gt, i915, i) {
> + intel_wakeref_t w;
> +
> + with_intel_runtime_pm_if_active(gt->uncore->rpm, w)
> + intel_gt_invalidate_tlbs(gt);
> + }
LGTM.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
How about an improvement, either immediately or as followup, to define per tile bound flags and so be able to avoid trashing innocent tiles?
Like:
i915_vma_bind:
set_bit(I915_BO_WAS_BOUND_BIT(vma->vm->gt->info.id), &vma->obj->flags);
__i915_gem_object_unset_pages:
for_each_gt(gt, i915, i) {
if (!test_and_clear_bit(I915_BO_WAS_BOUND_BIT(i), &obj->flags))
continue;
...
}
Regards,
Tvrtko
> }
>
> return pages;
prev parent reply other threads:[~2022-05-11 7:23 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-10 20:33 [Intel-gfx] [PATCH] drm/i915/gem: Flush TLBs for all the tiles Andi Shyti
2022-05-10 22:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-05-11 4:14 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-05-11 7:23 ` Tvrtko Ursulin [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2ecc20eb-a80c-8643-4cc8-8f9e18b5919d@linux.intel.com \
--to=tvrtko.ursulin@linux.intel.com \
--cc=andi.shyti@linux.intel.com \
--cc=chris@chris-wilson.co.uk \
--cc=dri-devel@lists.freedesktop.org \
--cc=intel-gfx@lists.freedesktop.org \
--cc=matthew.auld@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox