From: "Das, Nirmoy" <nirmoy.das@linux.intel.com>
To: "Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
"Das, Nirmoy" <nirmoy.das@intel.com>,
"joonas.lahtinen@linux.intel.com"
<joonas.lahtinen@linux.intel.com>,
"Hajda, Andrzej" <andrzej.hajda@intel.com>,
"jani.nikula@linux.intel.com" <jani.nikula@linux.intel.com>,
"tvrtko.ursulin@linux.intel.com" <tvrtko.ursulin@linux.intel.com>,
"andi.shyti@linux.intel.com" <andi.shyti@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/mtl: do not enable render power-gating on MTL
Date: Wed, 17 May 2023 17:36:33 +0200 [thread overview]
Message-ID: <300d9f0c-f74f-55f9-40b4-13b65c3b4584@linux.intel.com> (raw)
In-Reply-To: <e9e56f74e740c40884d4351cc2946f695691f782.camel@intel.com>
On 5/17/2023 5:25 PM, Vivi, Rodrigo wrote:
> On Wed, 2023-05-17 at 17:12 +0200, Das, Nirmoy wrote:
>> On 5/17/2023 3:59 PM, Andrzej Hajda wrote:
>>> Multiple CI tests fails with forcewake ack timeouts
>>> if render power gating is enabled.
>>> BSpec 52698 clearly states it should be 0 for MTL.
>>>
>>> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/4983
>>> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gt/intel_rc6.c | 5 +++--
>>> 1 file changed, 3 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c
>>> b/drivers/gpu/drm/i915/gt/intel_rc6.c
>>> index 908a3d0f2343f4..ebb2373dd73640 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>>> @@ -117,8 +117,9 @@ static void gen11_rc6_enable(struct intel_rc6
>>> *rc6)
>>> GEN6_RC_CTL_RC6_ENABLE |
>>> GEN6_RC_CTL_EI_MODE(1);
>>>
>>> - /* Wa_16011777198 - Render powergating must remain disabled
>>> */
>>> - if (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0)
>>> ||
>>> + /* Wa_16011777198 and BSpec 52698 - Render powergating must
>>> be off */
>> Nice catch!
> Indeed! What a mess in the workaround database.
> It is telling us that no_impact on MTL SKUs while we clearly needs
> that. I tried to reopen that and get that fixed in the hsds.
>
>
>> instead of bspec you could add Wa_14012655556.
> not actually.
> 16011777198 is the right lineage number for 14012655556.
> Besides, 14012655556 is for DG2 anyway.
>
> Let's keep the way Adrzej put with the BSPec reference besides the
> lineage.
Makes sense, didn't realize 14012655556 is much older.
Thanks!
>
>>
>>> + if (IS_METEORLAKE(gt->i915) ||
>>> + IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0)
>>> ||
>>> IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
>>> pg_enable =
>>> GEN9_MEDIA_PG_ENABLE |
>>>
>>> ---
>>> base-commit: 01d3dd92d1b71421f6ee85e1bea829e0a917d979
>>> change-id: 20230517-mtl_disable_render_pg-b9f9f1567f9e
>> ^ unwanted artifacts ? Otherwise this looks good to me.
>>
>> Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
> with the artifacts removed:
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
>
>>> Best regards,
next prev parent reply other threads:[~2023-05-17 15:36 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-17 13:59 [Intel-gfx] [PATCH] drm/i915/mtl: do not enable render power-gating on MTL Andrzej Hajda
2023-05-17 15:12 ` Das, Nirmoy
2023-05-17 15:25 ` Vivi, Rodrigo
2023-05-17 15:36 ` Das, Nirmoy [this message]
2023-05-17 20:09 ` Rodrigo Vivi
2023-05-18 14:04 ` Andi Shyti
2023-05-18 14:50 ` [Intel-gfx] [PATCH v2] " Andrzej Hajda
2023-05-18 15:09 ` Rodrigo Vivi
2023-05-18 15:33 ` Andrzej Hajda
2023-05-18 16:11 ` Rodrigo Vivi
2023-05-18 16:56 ` Andrzej Hajda
2023-05-17 15:27 ` [Intel-gfx] [PATCH] " Andrzej Hajda
2023-05-17 19:35 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
2023-05-17 21:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: do not enable render power-gating on MTL (rev2) Patchwork
2023-05-18 10:20 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2023-05-18 16:41 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/mtl: do not enable render power-gating on MTL (rev3) Patchwork
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