Re: [Intel-gfx] [PATCH] drm/i915/psr: Configure and Program IO buffer Wake and Fast Wake

["Souza, Jose" <jose.souza@intel.com>]

On Mon, 2020-10-12 at 17:18 +0300, Gwan-gyeong Mun wrote:
> As per b.spec 49274, the IO buffer Wake lines and Fast Wake lines can be
> calculated based on the following formula.
> 
>  IO buffer wake lines = ROUNDUP(50us / total line time in us)
>  Fast wake lines = ROUNDUP(32us / total line time in us)
>  For both fields limit the minimum to 7 lines and maximum to 12 lines
> 
> It calculates IO buffer Wake and Fast Wake based on b.spec 49274 and
> programs it.
> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Lee Shawn C <shawn.c.lee@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 67 +++++++++++++++++++-----
>  drivers/gpu/drm/i915/i915_drv.h          |  2 +
>  drivers/gpu/drm/i915/i915_reg.h          |  4 ++
>  3 files changed, 61 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8a9d0bdde1bf..36b397acddb3 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -538,19 +538,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	val |= intel_psr2_get_tp_time(intel_dp);
>  
> 
> 
> 
> 
> 
> 
> 
>  	if (INTEL_GEN(dev_priv) >= 12) {
> -		/*
> -		 * TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
> -		 * values from BSpec. In order to setting an optimal power
> -		 * consumption, lower than 4k resoluition mode needs to decrese
> -		 * IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution
> -		 * mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.
> -		 */
> -		val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
> -		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(7);
> -		val |= TGL_EDP_PSR2_FAST_WAKE(7);
> +		if (dev_priv->psr.io_buffer_wake < 9 || dev_priv->psr.fast_wake < 9)
> +			val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_2;
> +		else
> +			val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3;
> +		val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(dev_priv->psr.io_buffer_wake);
> +		val |= TGL_EDP_PSR2_FAST_WAKE(dev_priv->psr.fast_wake);
>  	} else if (INTEL_GEN(dev_priv) >= 9) {
> -		val |= EDP_PSR2_IO_BUFFER_WAKE(7);
> -		val |= EDP_PSR2_FAST_WAKE(7);
> +		val |= EDP_PSR2_IO_BUFFER_WAKE(dev_priv->psr.io_buffer_wake);
> +		val |= EDP_PSR2_FAST_WAKE(dev_priv->psr.fast_wake);
>  	}
>  
> 
> 
> 
> 
> 
> 
> 
>  	if (dev_priv->psr.psr2_sel_fetch_enabled) {
> @@ -810,6 +806,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
>  	int psr_setup_time;
> +	u32 io_buffer_wake = EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES;
> +	u32 fast_wake = EDP_PSR2_FAST_WAKE_MIN_LINES;

Those values set will always be overwritten, so should not be initialized.

>  
> 
> 
> 
> 
> 
> 
> 
>  	if (!CAN_PSR(dev_priv))
>  		return;
> @@ -859,6 +857,51 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
>  		return;
>  	}
>  
> 
> 
> 
> 
> 

All of the bellow should be in intel_psr2_config_valid() 

> +	/*
> +	 * B.Spec 49274
> +	 * IO buffer wake lines = ROUNDUP(50us / total line time in us)
> +	 * Fast wake lines = ROUNDUP(32us / total line time in us)
> +	 * For both fields limit the minimum to 7 lines and maximum to 12 lines
> +	 */

I always thought that the calculation here would use skl_wm_params->linetime_us.
io_buffer_wake = DIV_ROUND_UP(50, dev_priv->psr.wm_linetime_usec);

+ Ville here

> +	io_buffer_wake = intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 50);
> +	fast_wake = intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 32);
> +
> +	if (INTEL_GEN(dev_priv) >= 12) {
> +		if (io_buffer_wake < TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES ||
> +		    io_buffer_wake > TGL_EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES) {
> +			drm_dbg_kms(&dev_priv->drm,
> +				    "PSR condition failed: Invalid PSR2 IO Buffer Wake lines (%d)\n",
> +				    io_buffer_wake);

Moving to intel_psr2_config_valid() you can still allow PSR1 to be enabled.

> +			return;
> +		}
> +
> +		if (fast_wake < TGL_EDP_PSR2_FAST_WAKE_MIN_LINES ||
> +		    fast_wake > TGL_EDP_PSR2_FAST_WAKE_MAX_LINES) {
> +			drm_dbg_kms(&dev_priv->drm,
> +				    "PSR condition failed: Invalid PSR2 FAST Wake lines (%d)\n",
> +				    fast_wake);
> +			return;
> +		}
> +	} else if (INTEL_GEN(dev_priv) >= 9) {
> +		if (io_buffer_wake < EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES ||
> +		    io_buffer_wake > EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES) {
> +			drm_dbg_kms(&dev_priv->drm,
> +				    "PSR condition failed: Invalid PSR2 IO Buffer Wake lines (%d)\n",
> +				    io_buffer_wake);
> +			return;
> +		}
> +
> +		if (fast_wake < EDP_PSR2_FAST_WAKE_MIN_LINES ||
> +		    fast_wake > EDP_PSR2_FAST_WAKE_MAX_LINES) {
> +			drm_dbg_kms(&dev_priv->drm,
> +				    "PSR condition failed: Invalid PSR2 FAST Wake lines (%d)\n",
> +				    fast_wake);
> +			return;
> +		}
> +	}

Reuse the code above for gen12+ and gen9+ doing something like we do for psr_max_h/psr_max_w.

> +	dev_priv->psr.io_buffer_wake = io_buffer_wake < 7 ? 7 : io_buffer_wake;
> +	dev_priv->psr.fast_wake = fast_wake < 7 ? 7 : fast_wake;

Hardcoded. Please add those to i915_reg.h.

> +
>  	crtc_state->has_psr = true;
>  	crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state);
>  	crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index eef9a821c49c..767066bc387c 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -508,6 +508,8 @@ struct i915_psr {
>  	struct delayed_work dc3co_work;
>  	bool force_mode_changed;
>  	struct drm_dp_vsc_sdp vsc;
> +	u32 io_buffer_wake;
> +	u32 fast_wake;
>  };
>  
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
> 
>  #define QUIRK_LVDS_SSC_DISABLE (1<<1)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6ad9ee4243a0..8c98cdb8c438 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4547,14 +4547,18 @@ enum {
>  #define   EDP_MAX_SU_DISABLE_TIME(t)		((t) << 20)
>  #define   EDP_MAX_SU_DISABLE_TIME_MASK		(0x1f << 20)
>  #define   EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES	8
> +#define   EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES	5
>  #define   EDP_PSR2_IO_BUFFER_WAKE(lines)	((EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES - (lines)) << 13)
>  #define   EDP_PSR2_IO_BUFFER_WAKE_MASK		(3 << 13)
> +#define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MAX_LINES	12
>  #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES	5
>  #define   TGL_EDP_PSR2_IO_BUFFER_WAKE(lines)	(((lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) << 13)
>  #define   TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK	(7 << 13)
>  #define   EDP_PSR2_FAST_WAKE_MAX_LINES		8
> +#define   EDP_PSR2_FAST_WAKE_MIN_LINES		5
>  #define   EDP_PSR2_FAST_WAKE(lines)		((EDP_PSR2_FAST_WAKE_MAX_LINES - (lines)) << 11)
>  #define   EDP_PSR2_FAST_WAKE_MASK		(3 << 11)
> +#define   TGL_EDP_PSR2_FAST_WAKE_MAX_LINES	12
>  #define   TGL_EDP_PSR2_FAST_WAKE_MIN_LINES	5
>  #define   TGL_EDP_PSR2_FAST_WAKE(lines)		(((lines) - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES) << 10)
>  #define   TGL_EDP_PSR2_FAST_WAKE_MASK		(7 << 10)

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx