From: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Borislav Petkov <bp@suse.de>,
Alan Previn <alan.previn.teres.alexis@intel.com>,
David Airlie <airlied@linux.ie>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 10/21] drm/i915/guc: use kernel-doc for enum intel_guc_tlb_inval_mode
Date: Wed, 13 Jul 2022 10:30:07 +0100 [thread overview]
Message-ID: <39ff9de11bef9a30205fa340f89fa36de783be55.1657703926.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1657703926.git.mchehab@kernel.org>
Transform the comments for intel_guc_tlb_inval_mode into a
kernel-doc markup.
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---
See [PATCH 00/21] at: https://lore.kernel.org/all/cover.1657703926.git.mchehab@kernel.org/
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
index 2e39d8df4c82..14e35a2f8306 100644
--- a/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
+++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h
@@ -190,15 +190,18 @@ enum intel_guc_tlb_invalidation_type {
INTEL_GUC_TLB_INVAL_GUC = 0x3,
};
-/*
- * 0: Heavy mode of Invalidation:
+/**
+ * enum intel_guc_tlb_inval_mode - define the mode for TLB cache invlidation
+ *
+ * @INTEL_GUC_TLB_INVAL_MODE_HEAVY: Heavy Invalidation Mode.
* The pipeline of the engine(s) for which the invalidation is targeted to is
* blocked, and all the in-flight transactions are guaranteed to be Globally
- * Observed before completing the TLB invalidation
- * 1: Lite mode of Invalidation:
+ * Observed before completing the TLB invalidation.
+ * @INTEL_GUC_TLB_INVAL_MODE_LITE: Light Invalidation Mode.
* TLBs of the targeted engine(s) are immediately invalidated.
* In-flight transactions are NOT guaranteed to be Globally Observed before
* completing TLB invalidation.
+ *
* Light Invalidation Mode is to be used only when
* it can be guaranteed (by SW) that the address translations remain invariant
* for the in-flight transactions across the TLB invalidation. In other words,
--
2.36.1
next prev parent reply other threads:[~2022-07-13 9:30 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-13 9:29 [Intel-gfx] [PATCH 00/21] Fix performance regressions with TLB and add GuC support Mauro Carvalho Chehab
2022-07-13 9:29 ` [Intel-gfx] [PATCH 01/21] drm/i915/gt: Ignore TLB invalidations on idle engines Mauro Carvalho Chehab
2022-07-13 9:29 ` [Intel-gfx] [PATCH 02/21] drm/i915/gt: document with_intel_gt_pm_if_awake() Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 03/21] drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 04/21] drm/i915/gt: Only invalidate TLBs exposed to user manipulation Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 05/21] drm/i915/gt: Skip TLB invalidations once wedged Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 06/21] drm/i915/gt: Batch TLB invalidations Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 07/21] drm/i915/gt: describe the new tlb parameter at i915_vma_resource Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 08/21] drm/i915/gt: Move TLB invalidation to its own file Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 09/21] drm/i915/guc: Define CTB based TLB invalidation routines Mauro Carvalho Chehab
2022-07-13 9:30 ` Mauro Carvalho Chehab [this message]
2022-07-13 9:30 ` [Intel-gfx] [PATCH 11/21] drm/i915/guc: document the TLB invalidation struct members Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 12/21] drm/i915/guc: Introduce TLB_INVALIDATION_ALL action Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 13/21] drm/i915: Invalidate the TLBs on each GT Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 14/21] drm/i915: document tlb field at struct drm_i915_gem_object Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 15/21] drm/i915: Add platform macro for selective tlb flush Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 16/21] drm/i915: Define GuC Based TLB invalidation routines Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 17/21] drm/i915: Add generic interface for tlb invalidation for XeHP Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 18/21] drm/i915: Use selective tlb invalidations where supported Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 19/21] drm/i915/gt: document TLB cache invalidation functions Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 20/21] drm/i915/guc: describe enum intel_guc_tlb_invalidation_type Mauro Carvalho Chehab
2022-07-13 9:30 ` [Intel-gfx] [PATCH 21/21] drm/i915/guc: document TLB cache invalidation functions Mauro Carvalho Chehab
2022-07-13 9:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Fix performance regressions with TLB and add GuC support Patchwork
2022-07-13 13:13 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Fix performance regressions with TLB and add GuC support (rev2) Patchwork
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