From: "Kulkarni, Vandita" <vandita.kulkarni@intel.com>
To: "Lee, Shawn C" <shawn.c.lee@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "Nikula, Jani" <jani.nikula@intel.com>,
"Chiou, Cooper" <cooper.chiou@intel.com>,
"Tseng, William" <william.tseng@intel.com>
Subject: Re: [Intel-gfx] [V3 5/7] drm/i915: Get proper min cdclk if vDSC enabled
Date: Fri, 23 Jul 2021 07:06:21 +0000 [thread overview]
Message-ID: <494aeb6366334b7da222ef96bc6b3beb@intel.com> (raw)
In-Reply-To: <20210723070548.29315-6-shawn.c.lee@intel.com>
> -----Original Message-----
> From: Lee, Shawn C <shawn.c.lee@intel.com>
> Sent: Friday, July 23, 2021 12:36 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; ville.syrjala@linux.intel.com;
> Kulkarni, Vandita <vandita.kulkarni@intel.com>; Chiou, Cooper
> <cooper.chiou@intel.com>; Tseng, William <william.tseng@intel.com>; Lee,
> Shawn C <shawn.c.lee@intel.com>; Jani Nikula <jani.nikula@linux.intel.com>
> Subject: [V3 5/7] drm/i915: Get proper min cdclk if vDSC enabled
>
> VDSC engine can process only 1 pixel per Cd clock. In case VDSC is used and
> max slice count == 1, max supported pixel clock should be 100% of CD clock.
> Then do min_cdclk and pixel clock comparison to get proper min cdclk.
>
> v2:
> - Check for dsc enable and slice count ==1 then allow to
> double confirm min cdclk value.
LGTM,
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Cc: Cooper Chiou <cooper.chiou@intel.com>
> Cc: William Tseng <william.tseng@intel.com>
> Signed-off-by: Lee Shawn C <shawn.c.lee@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 71067a62264d..3e09f6370d27 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2159,6 +2159,16 @@ int intel_crtc_compute_min_cdclk(const struct
> intel_crtc_state *crtc_state)
> /* Account for additional needs from the planes */
> min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
>
> + /*
> + * VDSC engine can process only 1 pixel per Cd clock.
> + * In case VDSC is used and max slice count == 1,
> + * max supported pixel clock should be 100% of CD clock.
> + * Then do min_cdclk and pixel clock comparison to get cdclk.
> + */
> + if (crtc_state->dsc.compression_enable &&
> + crtc_state->dsc.slice_count == 1)
> + min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
> +
> /*
> * HACK. Currently for TGL platforms we calculate
> * min_cdclk initially based on pixel_rate divided
> --
> 2.17.1
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next prev parent reply other threads:[~2021-07-23 7:06 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-23 7:05 [Intel-gfx] [V3 0/7] MIPI DSI driver enhancements Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 1/7] drm/i915/dsi: send correct gpio_number on gen11 platform Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 2/7] drm/i915/jsl: program DSI panel GPIOs Lee Shawn C
2021-08-10 9:31 ` Jani Nikula
2021-08-10 10:04 ` Lee, Shawn C
2021-08-10 11:53 ` Jani Nikula
2021-08-11 1:50 ` Lee, Shawn C
2021-08-11 14:10 ` Lee, Shawn C
2021-08-12 14:52 ` Lee, Shawn C
2021-08-12 12:22 ` Jani Nikula
2021-07-23 7:05 ` [Intel-gfx] [V3 3/7] drm/i915/dsi: wait for header and payload credit available Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 4/7] drm/i915/dsi: refine send MIPI DCS command sequence Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 5/7] drm/i915: Get proper min cdclk if vDSC enabled Lee Shawn C
2021-07-23 7:06 ` Kulkarni, Vandita [this message]
2021-07-23 7:05 ` [Intel-gfx] [V3 6/7] drm/i915/dsi: Retrieve max brightness level from VBT Lee Shawn C
2021-07-23 7:05 ` [Intel-gfx] [V3 7/7] drm/i915/dsi: Send proper brightness value via MIPI DCS command Lee Shawn C
2021-07-23 11:14 ` kernel test robot
2021-07-26 6:54 ` [Intel-gfx] [v2] " Lee Shawn C
2021-07-23 7:39 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev3) Patchwork
2021-07-23 7:40 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-23 8:09 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-23 12:57 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-26 6:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for MIPI DSI driver enhancements (rev4) Patchwork
2021-07-26 6:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-07-26 7:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-07-26 9:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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