From: John Harrison <john.c.harrison@intel.com>
To: Matthew Brost <matthew.brost@intel.com>,
<intel-gfx@lists.freedesktop.org>,
<dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 15/51] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC
Date: Mon, 19 Jul 2021 18:03:05 -0700 [thread overview]
Message-ID: <4bfe5983-eb17-6993-6210-0f7fe38ea1fb@intel.com> (raw)
In-Reply-To: <20210716201724.54804-16-matthew.brost@intel.com>
On 7/16/2021 13:16, Matthew Brost wrote:
> When running the GuC the GPU can't be considered idle if the GuC still
> has contexts pinned. As such, a call has been added in
> intel_gt_wait_for_idle to idle the UC and in turn the GuC by waiting for
> the number of unpinned contexts to go to zero.
>
> v2: rtimeout -> remaining_timeout
> v3: Drop unnecessary includes, guc_submission_busy_loop ->
> guc_submission_send_busy_loop, drop negatie timeout trick, move a
> refactor of guc_context_unpin to earlier path (John H)
>
> Cc: John Harrison <john.c.harrison@intel.com>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_mman.c | 3 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 19 +++++
> drivers/gpu/drm/i915/gt/intel_gt.h | 2 +
> drivers/gpu/drm/i915/gt/intel_gt_requests.c | 21 ++---
> drivers/gpu/drm/i915/gt/intel_gt_requests.h | 7 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc.h | 4 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 1 +
> drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 4 +
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 85 +++++++++++++++++--
> drivers/gpu/drm/i915/gt/uc/intel_uc.h | 5 ++
> drivers/gpu/drm/i915/i915_gem_evict.c | 1 +
> .../gpu/drm/i915/selftests/igt_live_test.c | 2 +-
> .../gpu/drm/i915/selftests/mock_gem_device.c | 3 +-
> 13 files changed, 129 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> index a90f796e85c0..6fffd4d377c2 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> @@ -645,7 +645,8 @@ mmap_offset_attach(struct drm_i915_gem_object *obj,
> goto insert;
>
> /* Attempt to reap some mmap space from dead objects */
> - err = intel_gt_retire_requests_timeout(&i915->gt, MAX_SCHEDULE_TIMEOUT);
> + err = intel_gt_retire_requests_timeout(&i915->gt, MAX_SCHEDULE_TIMEOUT,
> + NULL);
> if (err)
> goto err;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index e714e21c0a4d..acfdd53b2678 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -585,6 +585,25 @@ static void __intel_gt_disable(struct intel_gt *gt)
> GEM_BUG_ON(intel_gt_pm_is_awake(gt));
> }
>
> +int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
> +{
> + long remaining_timeout;
> +
> + /* If the device is asleep, we have no requests outstanding */
> + if (!intel_gt_pm_is_awake(gt))
> + return 0;
> +
> + while ((timeout = intel_gt_retire_requests_timeout(gt, timeout,
> + &remaining_timeout)) > 0) {
> + cond_resched();
> + if (signal_pending(current))
> + return -EINTR;
> + }
> +
> + return timeout ? timeout : intel_uc_wait_for_idle(>->uc,
> + remaining_timeout);
> +}
> +
> int intel_gt_init(struct intel_gt *gt)
> {
> int err;
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
> index e7aabe0cc5bf..74e771871a9b 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.h
> @@ -48,6 +48,8 @@ void intel_gt_driver_release(struct intel_gt *gt);
>
> void intel_gt_driver_late_release(struct intel_gt *gt);
>
> +int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
> +
> void intel_gt_check_and_clear_faults(struct intel_gt *gt);
> void intel_gt_clear_error_registers(struct intel_gt *gt,
> intel_engine_mask_t engine_mask);
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.c b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> index 647eca9d867a..edb881d75630 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.c
> @@ -130,7 +130,8 @@ void intel_engine_fini_retire(struct intel_engine_cs *engine)
> GEM_BUG_ON(engine->retire);
> }
>
> -long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout)
> +long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout,
> + long *remaining_timeout)
> {
> struct intel_gt_timelines *timelines = >->timelines;
> struct intel_timeline *tl, *tn;
> @@ -195,22 +196,10 @@ out_active: spin_lock(&timelines->lock);
> if (flush_submission(gt, timeout)) /* Wait, there's more! */
> active_count++;
>
> - return active_count ? timeout : 0;
> -}
> -
> -int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout)
> -{
> - /* If the device is asleep, we have no requests outstanding */
> - if (!intel_gt_pm_is_awake(gt))
> - return 0;
> -
> - while ((timeout = intel_gt_retire_requests_timeout(gt, timeout)) > 0) {
> - cond_resched();
> - if (signal_pending(current))
> - return -EINTR;
> - }
> + if (remaining_timeout)
> + *remaining_timeout = timeout;
>
> - return timeout;
> + return active_count ? timeout : 0;
> }
>
> static void retire_work_handler(struct work_struct *work)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_requests.h b/drivers/gpu/drm/i915/gt/intel_gt_requests.h
> index fcc30a6e4fe9..83ff5280c06e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_requests.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_requests.h
You were saying the the include of stddef is needed here?
> @@ -10,10 +10,11 @@ struct intel_engine_cs;
> struct intel_gt;
> struct intel_timeline;
>
> -long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout);
> +long intel_gt_retire_requests_timeout(struct intel_gt *gt, long timeout,
> + long *remaining_timeout);
> static inline void intel_gt_retire_requests(struct intel_gt *gt)
> {
> - intel_gt_retire_requests_timeout(gt, 0);
> + intel_gt_retire_requests_timeout(gt, 0, NULL);
> }
>
> void intel_engine_init_retire(struct intel_engine_cs *engine);
> @@ -21,8 +22,6 @@ void intel_engine_add_retire(struct intel_engine_cs *engine,
> struct intel_timeline *tl);
> void intel_engine_fini_retire(struct intel_engine_cs *engine);
>
> -int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
> -
> void intel_gt_init_requests(struct intel_gt *gt);
> void intel_gt_park_requests(struct intel_gt *gt);
> void intel_gt_unpark_requests(struct intel_gt *gt);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> index 80b88bae5f24..3cc566565224 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
> @@ -39,6 +39,8 @@ struct intel_guc {
> spinlock_t irq_lock;
> unsigned int msg_enabled_mask;
>
> + atomic_t outstanding_submission_g2h;
> +
> struct {
> void (*reset)(struct intel_guc *guc);
> void (*enable)(struct intel_guc *guc);
> @@ -238,6 +240,8 @@ static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
> spin_unlock_irq(&guc->irq_lock);
> }
>
> +int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout);
> +
> int intel_guc_reset_engine(struct intel_guc *guc,
> struct intel_engine_cs *engine);
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> index c33906ec478d..f1cbed6b9f0a 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c
> @@ -109,6 +109,7 @@ void intel_guc_ct_init_early(struct intel_guc_ct *ct)
> INIT_LIST_HEAD(&ct->requests.incoming);
> INIT_WORK(&ct->requests.worker, ct_incoming_request_worker_func);
> tasklet_setup(&ct->receive_tasklet, ct_receive_tasklet_func);
> + init_waitqueue_head(&ct->wq);
> }
>
> static inline const char *guc_ct_buffer_type_to_str(u32 type)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> index 785dfc5c6efb..4b30a562ae63 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h
> @@ -10,6 +10,7 @@
> #include <linux/spinlock.h>
> #include <linux/workqueue.h>
> #include <linux/ktime.h>
> +#include <linux/wait.h>
>
> #include "intel_guc_fwif.h"
>
> @@ -68,6 +69,9 @@ struct intel_guc_ct {
>
> struct tasklet_struct receive_tasklet;
>
> + /** @wq: wait queue for g2h chanenl */
> + wait_queue_head_t wq;
> +
> struct {
> u16 last_fence; /* last fence used to send request */
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index f7e34baa9506..088d11e2e497 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -254,6 +254,69 @@ static inline void set_lrc_desc_registered(struct intel_guc *guc, u32 id,
> xa_store_irq(&guc->context_lookup, id, ce, GFP_ATOMIC);
> }
>
> +static int guc_submission_send_busy_loop(struct intel_guc* guc,
> + const u32 *action,
> + u32 len,
> + u32 g2h_len_dw,
> + bool loop)
> +{
> + int err;
> +
> + err = intel_guc_send_busy_loop(guc, action, len, g2h_len_dw, loop);
> +
> + if (!err && g2h_len_dw)
> + atomic_inc(&guc->outstanding_submission_g2h);
> +
> + return err;
> +}
> +
> +static int guc_wait_for_pending_msg(struct intel_guc *guc,
> + atomic_t *wait_var,
> + bool interruptible,
> + long timeout)
> +{
> + const int state = interruptible ?
> + TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
> + DEFINE_WAIT(wait);
> +
> + might_sleep();
> + GEM_BUG_ON(timeout < 0);
> +
> + if (!atomic_read(wait_var))
> + return 0;
> +
> + if (!timeout)
> + return -ETIME;
> +
> + for (;;) {
> + prepare_to_wait(&guc->ct.wq, &wait, state);
> +
> + if (!atomic_read(wait_var))
> + break;
> +
> + if (signal_pending_state(state, current)) {
> + timeout = -EINTR;
> + break;
> + }
> +
> + if (!timeout) {
> + timeout = -ETIME;
> + break;
> + }
> +
> + timeout = io_schedule_timeout(timeout);
> + }
> + finish_wait(&guc->ct.wq, &wait);
> +
> + return (timeout < 0) ? timeout : 0;
> +}
> +
> +int intel_guc_wait_for_idle(struct intel_guc *guc, long timeout)
> +{
> + return guc_wait_for_pending_msg(guc, &guc->outstanding_submission_g2h,
> + true, timeout);
> +}
> +
> static int guc_add_request(struct intel_guc *guc, struct i915_request *rq)
> {
> int err;
> @@ -280,6 +343,7 @@ static int guc_add_request(struct intel_guc *guc, struct i915_request *rq)
>
> err = intel_guc_send_nb(guc, action, len, g2h_len_dw);
> if (!enabled && !err) {
> + atomic_inc(&guc->outstanding_submission_g2h);
> set_context_enabled(ce);
> } else if (!enabled) {
> clr_context_pending_enable(ce);
> @@ -731,7 +795,8 @@ static int __guc_action_register_context(struct intel_guc *guc,
> offset,
> };
>
> - return intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action), 0, true);
> + return guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action),
> + 0, true);
> }
>
> static int register_context(struct intel_context *ce)
> @@ -751,8 +816,9 @@ static int __guc_action_deregister_context(struct intel_guc *guc,
> guc_id,
> };
>
> - return intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action),
> - G2H_LEN_DW_DEREGISTER_CONTEXT, true);
> + return guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action),
> + G2H_LEN_DW_DEREGISTER_CONTEXT,
> + true);
> }
>
> static int deregister_context(struct intel_context *ce, u32 guc_id)
> @@ -893,8 +959,8 @@ static void __guc_context_sched_disable(struct intel_guc *guc,
>
> intel_context_get(ce);
>
> - intel_guc_send_busy_loop(guc, action, ARRAY_SIZE(action),
> - G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, true);
> + guc_submission_send_busy_loop(guc, action, ARRAY_SIZE(action),
> + G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, true);
> }
>
> static u16 prep_context_pending_disable(struct intel_context *ce)
> @@ -1440,6 +1506,12 @@ g2h_context_lookup(struct intel_guc *guc, u32 desc_idx)
> return ce;
> }
>
> +static void decr_outstanding_submission_g2h(struct intel_guc *guc)
> +{
> + if (atomic_dec_and_test(&guc->outstanding_submission_g2h))
> + wake_up_all(&guc->ct.wq);
> +}
> +
> int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
> const u32 *msg,
> u32 len)
> @@ -1475,6 +1547,8 @@ int intel_guc_deregister_done_process_msg(struct intel_guc *guc,
> lrc_destroy(&ce->ref);
> }
>
> + decr_outstanding_submission_g2h(guc);
> +
> return 0;
> }
>
> @@ -1523,6 +1597,7 @@ int intel_guc_sched_done_process_msg(struct intel_guc *guc,
> spin_unlock_irqrestore(&ce->guc_state.lock, flags);
> }
>
> + decr_outstanding_submission_g2h(guc);
> intel_context_put(ce);
>
> return 0;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.h b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> index 9c954c589edf..c4cef885e984 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.h
> @@ -81,6 +81,11 @@ uc_state_checkers(guc, guc_submission);
> #undef uc_state_checkers
> #undef __uc_state_checker
>
> +static inline int intel_uc_wait_for_idle(struct intel_uc *uc, long timeout)
> +{
> + return intel_guc_wait_for_idle(&uc->guc, timeout);
> +}
> +
> #define intel_uc_ops_function(_NAME, _OPS, _TYPE, _RET) \
> static inline _TYPE intel_uc_##_NAME(struct intel_uc *uc) \
> { \
> diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c
> index 4d2d59a9942b..2b73ddb11c66 100644
> --- a/drivers/gpu/drm/i915/i915_gem_evict.c
> +++ b/drivers/gpu/drm/i915/i915_gem_evict.c
> @@ -27,6 +27,7 @@
> */
>
> #include "gem/i915_gem_context.h"
> +#include "gt/intel_gt.h"
Still not seeing a need for this.
> #include "gt/intel_gt_requests.h"
>
> #include "i915_drv.h"
> diff --git a/drivers/gpu/drm/i915/selftests/igt_live_test.c b/drivers/gpu/drm/i915/selftests/igt_live_test.c
> index c130010a7033..1c721542e277 100644
> --- a/drivers/gpu/drm/i915/selftests/igt_live_test.c
> +++ b/drivers/gpu/drm/i915/selftests/igt_live_test.c
> @@ -5,7 +5,7 @@
> */
>
> #include "i915_drv.h"
> -#include "gt/intel_gt_requests.h"
> +#include "gt/intel_gt.h"
Nor this.
John.
>
> #include "../i915_selftest.h"
> #include "igt_flush_test.h"
> diff --git a/drivers/gpu/drm/i915/selftests/mock_gem_device.c b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> index d189c4bd4bef..4f8180146888 100644
> --- a/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> +++ b/drivers/gpu/drm/i915/selftests/mock_gem_device.c
> @@ -52,7 +52,8 @@ void mock_device_flush(struct drm_i915_private *i915)
> do {
> for_each_engine(engine, gt, id)
> mock_engine_flush(engine);
> - } while (intel_gt_retire_requests_timeout(gt, MAX_SCHEDULE_TIMEOUT));
> + } while (intel_gt_retire_requests_timeout(gt, MAX_SCHEDULE_TIMEOUT,
> + NULL));
> }
>
> static void mock_device_release(struct drm_device *dev)
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next prev parent reply other threads:[~2021-07-20 1:03 UTC|newest]
Thread overview: 111+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-16 20:16 [Intel-gfx] [PATCH 00/51] GuC submission support Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 01/51] drm/i915/guc: Add new GuC interface defines and structures Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 02/51] drm/i915/guc: Remove GuC stage descriptor, add LRC descriptor Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 03/51] drm/i915/guc: Add LRC descriptor context lookup array Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 04/51] drm/i915/guc: Implement GuC submission tasklet Matthew Brost
2021-07-19 23:01 ` John Harrison
2021-07-19 22:55 ` Matthew Brost
2021-07-20 0:26 ` John Harrison
2021-07-16 20:16 ` [Intel-gfx] [PATCH 05/51] drm/i915/guc: Add bypass tasklet submission path to GuC Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 06/51] drm/i915/guc: Implement GuC context operations for new inteface Matthew Brost
2021-07-20 0:23 ` John Harrison
2021-07-20 2:45 ` Matthew Brost
2021-07-20 0:51 ` Daniele Ceraolo Spurio
2021-07-20 4:04 ` Matthew Brost
2021-07-21 23:51 ` Daniele Ceraolo Spurio
2021-07-22 7:57 ` Michal Wajdeczko
2021-07-22 15:48 ` Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 07/51] drm/i915/guc: Insert fence on context when deregistering Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 08/51] drm/i915/guc: Defer context unpin until scheduling is disabled Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 09/51] drm/i915/guc: Disable engine barriers with GuC during unpin Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 10/51] drm/i915/guc: Extend deregistration fence to schedule disable Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 11/51] drm/i915: Disable preempt busywait when using GuC scheduling Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 12/51] drm/i915/guc: Ensure request ordering via completion fences Matthew Brost
2021-07-19 23:46 ` Daniele Ceraolo Spurio
2021-07-20 2:48 ` Matthew Brost
2021-07-20 2:50 ` Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 13/51] drm/i915/guc: Disable semaphores when using GuC scheduling Matthew Brost
2021-07-20 0:33 ` John Harrison
2021-07-16 20:16 ` [Intel-gfx] [PATCH 14/51] drm/i915/guc: Ensure G2H response has space in buffer Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 15/51] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC Matthew Brost
2021-07-20 1:03 ` John Harrison [this message]
2021-07-20 1:53 ` Matthew Brost
2021-07-20 19:49 ` John Harrison
2021-07-16 20:16 ` [Intel-gfx] [PATCH 16/51] drm/i915/guc: Update GuC debugfs to support new GuC Matthew Brost
2021-07-20 1:13 ` John Harrison
2021-07-16 20:16 ` [Intel-gfx] [PATCH 17/51] drm/i915/guc: Add several request trace points Matthew Brost
2021-07-20 1:27 ` John Harrison
2021-07-20 2:10 ` Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 18/51] drm/i915: Add intel_context tracing Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 19/51] drm/i915/guc: GuC virtual engines Matthew Brost
2021-07-19 23:33 ` Daniele Ceraolo Spurio
2021-07-19 23:27 ` Matthew Brost
2021-07-19 23:42 ` Daniele Ceraolo Spurio
2021-07-19 23:32 ` Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 20/51] drm/i915: Track 'serial' counts for " Matthew Brost
2021-07-20 1:28 ` John Harrison
2021-07-20 1:54 ` Matthew Brost
2021-07-20 16:47 ` Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 21/51] drm/i915: Hold reference to intel_context over life of i915_request Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 22/51] drm/i915/guc: Disable bonding extension with GuC submission Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 23/51] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs Matthew Brost
2021-07-20 19:45 ` John Harrison
2021-07-22 12:46 ` Tvrtko Ursulin
2021-07-26 22:25 ` Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 24/51] drm/i915: Add i915_sched_engine destroy vfunc Matthew Brost
2021-07-20 19:55 ` John Harrison
2021-07-20 19:53 ` Matthew Brost
2021-07-16 20:16 ` [Intel-gfx] [PATCH 25/51] drm/i915: Move active request tracking to a vfunc Matthew Brost
2021-07-20 20:05 ` John Harrison
2021-07-16 20:16 ` [Intel-gfx] [PATCH 26/51] drm/i915/guc: Reset implementation for new GuC interface Matthew Brost
2021-07-20 20:19 ` John Harrison
2021-07-20 20:59 ` Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 27/51] drm/i915: Reset GPU immediately if submission is disabled Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 28/51] drm/i915/guc: Add disable interrupts to guc sanitize Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 29/51] drm/i915/guc: Suspend/resume implementation for new interface Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 30/51] drm/i915/guc: Handle context reset notification Matthew Brost
2021-07-20 20:29 ` John Harrison
2021-07-20 20:38 ` Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 31/51] drm/i915/guc: Handle engine reset failure notification Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 32/51] drm/i915/guc: Enable the timer expired interrupt for GuC Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 33/51] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Matthew Brost
2021-07-22 4:47 ` Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 34/51] drm/i915/guc: Don't complain about reset races Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 35/51] drm/i915/guc: Enable GuC engine reset Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 36/51] drm/i915/guc: Capture error state on context reset Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 37/51] drm/i915/guc: Fix for error capture after full GPU reset with GuC Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 38/51] drm/i915/guc: Hook GuC scheduling policies up Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 39/51] drm/i915/guc: Connect reset modparam updates to GuC policy flags Matthew Brost
2021-07-16 20:04 ` Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 40/51] drm/i915/guc: Include scheduling policies in the debugfs state dump Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 41/51] drm/i915/guc: Add golden context to GuC ADS Matthew Brost
2021-07-19 17:24 ` Matthew Brost
2021-07-19 18:25 ` John Harrison
2021-07-19 18:30 ` Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 42/51] drm/i915/guc: Implement banned contexts for GuC submission Matthew Brost
2021-07-20 21:41 ` John Harrison
2021-07-16 20:17 ` [Intel-gfx] [PATCH 43/51] drm/i915/guc: Support request cancellation Matthew Brost
2021-07-22 19:56 ` Daniele Ceraolo Spurio
2021-07-22 20:13 ` Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 44/51] drm/i915/selftest: Better error reporting from hangcheck selftest Matthew Brost
2021-07-16 20:13 ` Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 45/51] drm/i915/selftest: Fix workarounds selftest for GuC submission Matthew Brost
2021-07-20 17:14 ` Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 46/51] drm/i915/selftest: Fix MOCS " Matthew Brost
2021-07-16 23:57 ` Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 47/51] drm/i915/selftest: Increase some timeouts in live_requests Matthew Brost
2021-07-20 21:46 ` John Harrison
2021-07-22 8:13 ` Tvrtko Ursulin
2021-07-16 20:17 ` [Intel-gfx] [PATCH 48/51] drm/i915/selftest: Fix hangcheck self test for GuC submission Matthew Brost
2021-07-16 23:43 ` Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 49/51] drm/i915/selftest: Bump selftest timeouts for hangcheck Matthew Brost
2021-07-16 22:23 ` Matthew Brost
2021-07-22 8:17 ` Tvrtko Ursulin
2021-07-16 20:17 ` [Intel-gfx] [PATCH 50/51] drm/i915/guc: Implement GuC priority management Matthew Brost
2021-07-22 20:26 ` Daniele Ceraolo Spurio
2021-07-22 21:38 ` Matthew Brost
2021-07-22 21:50 ` Daniele Ceraolo Spurio
2021-07-22 21:55 ` Matthew Brost
2021-07-16 20:17 ` [Intel-gfx] [PATCH 51/51] drm/i915/guc: Unblock GuC submission on Gen11+ Matthew Brost
2021-07-17 1:10 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission support (rev3) Patchwork
2021-07-19 9:06 ` [Intel-gfx] [PATCH 00/51] GuC submission support Tvrtko Ursulin
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