Re: [Intel-gfx] [PATCH v4 1/2] drm/i915: Add support for LMEM PCIe resizable bar

["Das, Nirmoy" <nirmoy.das@intel.com>]

[-- Attachment #1: Type: text/plain, Size: 4662 bytes --]


On 7/10/2022 7:29 PM, priyanka.dandamudi@intel.com wrote:
> From: Akeem G Abodunrin<akeem.g.abodunrin@intel.com>
>
> Add support for the local memory PICe resizable bar, so that
> local memory can be resized to the maximum size supported by the device,
> and mapped correctly to the PCIe memory bar. It is usual that GPU
> devices expose only 256MB BARs primarily to be compatible with 32-bit
> systems. So, those devices cannot claim larger memory BAR windows size due
> to the system BIOS limitation. With this change, it would be possible to
> reprogram the windows of the bridge directly above the requesting device
> on the same BAR type.
>
> v2:Moved code to gt/intel_region_lmem.c and used only
> single underscore for function names.(Jani)
>
> v3: Optimised code.
>
> Signed-off-by: Akeem G Abodunrin<akeem.g.abodunrin@intel.com>
> Signed-off-by: Michał Winiarski<michal.winiarski@intel.com>
> Cc: Stuart Summers<stuart.summers@intel.com>
> Cc: Michael J Ruhl<michael.j.ruhl@intel.com>
> Cc: Prathap Kumar Valsan<prathap.kumar.valsan@intel.com>
> Cc: Jani Nikula<jani.nikula@intel.com>
> Signed-off-by: Priyanka Dandamudi<priyanka.dandamudi@intel.com>
> Reviewed-by: Matthew Auld<matthew.auld@intel.com>

|Reviewed-by: Nirmoy Das<nirmoy.das@intel.com>|

> ---
>   drivers/gpu/drm/i915/gt/intel_region_lmem.c | 75 +++++++++++++++++++++
>   1 file changed, 75 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> index fa7b86f83e7b..129e5d8b080d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> +++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c
> @@ -15,6 +15,79 @@
>   #include "gt/intel_gt_mcr.h"
>   #include "gt/intel_gt_regs.h"
>   
> +static void _release_bars(struct pci_dev *pdev)
> +{
> +	int resno;
> +
> +	for (resno = PCI_STD_RESOURCES; resno < PCI_STD_RESOURCE_END; resno++) {
> +		if (pci_resource_len(pdev, resno))
> +			pci_release_resource(pdev, resno);
> +	}
> +}
> +
> +static void
> +_resize_bar(struct drm_i915_private *i915, int resno, resource_size_t size)
> +{
> +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> +	int bar_size = pci_rebar_bytes_to_size(size);
> +	int ret;
> +
> +	_release_bars(pdev);
> +
> +	ret = pci_resize_resource(pdev, resno, bar_size);
> +	if (ret) {
> +		drm_info(&i915->drm, "Failed to resize BAR%d to %dM (%pe)\n",
> +			 resno, 1 << bar_size, ERR_PTR(ret));
> +		return;
> +	}
> +
> +	drm_info(&i915->drm, "BAR%d resized to %dM\n", resno, 1 << bar_size);
> +}
> +
> +#define LMEM_BAR_NUM 2
> +static void i915_resize_lmem_bar(struct drm_i915_private *i915, resource_size_t lmem_size)
> +{
> +	struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> +	struct pci_bus *root = pdev->bus;
> +	struct resource *root_res;
> +	resource_size_t rebar_size;
> +	u32 pci_cmd;
> +	int i;
> +
> +	rebar_size = roundup_pow_of_two(pci_resource_len(pdev, LMEM_BAR_NUM));
> +
> +	if (rebar_size != roundup_pow_of_two(lmem_size))
> +		rebar_size = lmem_size;
> +	else
> +		return;
> +
> +	/* Find out if root bus contains 64bit memory addressing */
> +	while (root->parent)
> +		root = root->parent;
> +
> +	pci_bus_for_each_resource(root, root_res, i) {
> +		if (root_res && root_res->flags & (IORESOURCE_MEM |
> +					IORESOURCE_MEM_64) && root_res->start > 0x100000000ull)
> +			break;
> +	}
> +
> +	/* pci_resize_resource will fail anyways */
> +	if (!root_res) {
> +		drm_info(&i915->drm, "Can't resize LMEM BAR - platform support is missing\n");
> +		return;
> +	}
> +
> +	/* First disable PCI memory decoding references */
> +	pci_read_config_dword(pdev, PCI_COMMAND, &pci_cmd);
> +	pci_write_config_dword(pdev, PCI_COMMAND,
> +			       pci_cmd & ~PCI_COMMAND_MEMORY);
> +
> +	_resize_bar(i915, LMEM_BAR_NUM, rebar_size);
> +
> +	pci_assign_unassigned_bus_resources(pdev->bus);
> +	pci_write_config_dword(pdev, PCI_COMMAND, pci_cmd);
> +}
> +
>   static int
>   region_lmem_release(struct intel_memory_region *mem)
>   {
> @@ -128,6 +201,8 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)
>   		lmem_size = intel_uncore_read64(&i915->uncore, GEN12_GSMBASE);
>   	}
>   
> +	i915_resize_lmem_bar(i915, lmem_size);
> +
>   	if (i915->params.lmem_size > 0) {
>   		lmem_size = min_t(resource_size_t, lmem_size,
>   				  mul_u32_u32(i915->params.lmem_size, SZ_1M));
Intel Deutschland GmbH
Registered Address: Am Campeon 10, 85579 Neubiberg, Germany
Tel: +49 89 99 8853-0, www.intel.de <http://www.intel.de>
Managing Directors: Christin Eisenschmid, Sharon Heck, Tiffany Doon Silva  
Chairperson of the Supervisory Board: Nicole Lau
Registered Office: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928

[-- Attachment #2: Type: text/html, Size: 6185 bytes --]