Re: [PATCH v2 2/2] drm/i915/ltphy: Return lowest portclock for HDMI from reverse algorithm

["Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>]

On 11/7/2025 3:05 PM, Suraj Kandpal wrote:
> Return the lowest port clock for HDMI when the reverse algorithm
> calculates it to be 0 to avoid errors later but throw a warn.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>
> v1 -> v2:
> -Derive intel_display in first line (Ankit)
> -Use the actual lowest clock from table (Ankit)
>
>   drivers/gpu/drm/i915/display/intel_lt_phy.c | 14 ++++++++++----
>   1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 57a0f443eb1a..1a7dc0ebd050 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -1671,7 +1671,7 @@ intel_lt_phy_calculate_hdmi_state(struct intel_lt_phy_pll_state *lt_state,
>   }
>   
>   static int
> -intel_lt_phy_calc_hdmi_port_clock(const struct intel_lt_phy_pll_state *lt_state)
> +intel_lt_phy_calc_hdmi_port_clock(const struct intel_crtc_state *crtc_state)
>   {
>   #define REGVAL(i) (				\
>   	(lt_state->data[i][3])		|	\
> @@ -1680,6 +1680,9 @@ intel_lt_phy_calc_hdmi_port_clock(const struct intel_lt_phy_pll_state *lt_state)
>   	(lt_state->data[i][0] << 24)		\
>   )
>   
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	const struct intel_lt_phy_pll_state *lt_state =
> +		&crtc_state->dpll_hw_state.ltpll;
>   	int clk = 0;
>   	u32 d8, pll_reg_5, pll_reg_3, pll_reg_57, m2div_frac, m2div_int;
>   	u64 temp0, temp1;
> @@ -1722,11 +1725,14 @@ intel_lt_phy_calc_hdmi_port_clock(const struct intel_lt_phy_pll_state *lt_state)
>   	 * frequency = (m2div * refclk_khz / (d8 * 10))
>   	 */
>   	d8 = (pll_reg_57 & REG_GENMASK(14, 7)) >> 7;
> +	if (d8 == 0) {
> +		drm_WARN_ON(display->drm,
> +			    "Invalid port clock using lowest HDMI portclock\n");
> +		return xe3plpd_lt_hdmi_252.clock;
> +	}
>   	m2div_int = (pll_reg_3  & REG_GENMASK(14, 5)) >> 5;
>   	temp0 = ((u64)m2div_frac * REF_CLK_KHZ) >> 32;
>   	temp1 = (u64)m2div_int * REF_CLK_KHZ;
> -	if (d8 == 0)
> -		return 0;
>   
>   	clk = div_u64((temp1 + temp0), d8 * 10);
>   
> @@ -1755,7 +1761,7 @@ intel_lt_phy_calc_port_clock(struct intel_encoder *encoder,
>   				      lt_state->config[0]);
>   		clk = intel_lt_phy_get_dp_clock(rate);
>   	} else {
> -		clk = intel_lt_phy_calc_hdmi_port_clock(lt_state);
> +		clk = intel_lt_phy_calc_hdmi_port_clock(crtc_state);
>   	}
>   
>   	return clk;