From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915: CTS fixes (rev3)
Date: Tue, 25 Jun 2019 16:24:42 +0300 [thread overview]
Message-ID: <54b14c81-a39e-17c3-d427-4448cb6ddb05@intel.com> (raw)
In-Reply-To: <156146846599.2637.13053954922721421324@skylake-alporthouse-com>
On 25/06/2019 16:14, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2019-06-25 14:09:57)
>> Anybody knows whether the selftests are dealing with read only
>> whitelisted registers?
>> I'm not quite sure what can be tested with those (unless you can
>> exercise the 3d pipeline in this case).
> John added a hack:
>
> static bool ro_register(u32 reg)
> {
> if (reg & RING_FORCE_TO_NONPRIV_RD)
> return true;
>
> return false;
> }
>
> to ignore them. It is not clear why that did not take.
> -Chris
>
Oh...
That seems broken for a read only register and a default value of 0 :
static bool result_neq(struct intel_engine_cs *engine,
u32 a, u32 b, i915_reg_t reg)
{
if (a == b && !writeonly_reg(engine->i915, reg)) {
pr_err("Whitelist register 0x%4x:%08x was unwritable\n",
i915_mmio_reg_offset(reg), a);
return false;
}
return true;
}
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next prev parent reply other threads:[~2019-06-25 13:24 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-25 10:58 [PATCH v3 0/2] drm/i915: CTS fixes Lionel Landwerlin
2019-06-25 10:58 ` [PATCH v3 1/2] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT Lionel Landwerlin
2019-06-25 10:58 ` [PATCH v3 2/2] drm/i915/icl: " Lionel Landwerlin
2019-06-25 12:15 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: CTS fixes (rev3) Patchwork
2019-06-25 12:57 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-06-25 13:09 ` Lionel Landwerlin
2019-06-25 13:14 ` Chris Wilson
2019-06-25 13:24 ` Lionel Landwerlin [this message]
2019-06-25 13:28 ` Chris Wilson
2019-06-25 13:16 ` Chris Wilson
2019-06-25 13:19 ` Lionel Landwerlin
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