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From: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2 6/6] drm/i915: Set DP min_bpp to 8*3 for non-RGB output formats
Date: Tue, 09 Apr 2019 14:04:01 -0700	[thread overview]
Message-ID: <54c9028d5472f8c447b18063ab240eca315df3df.camel@intel.com> (raw)
In-Reply-To: <20190409203827.GE3888@intel.com>

On Tue, 2019-04-09 at 23:38 +0300, Ville Syrjälä wrote:
> On Tue, Apr 09, 2019 at 01:28:18PM -0700, Dhinakaran Pandiyan wrote:
> > On Tue, 2019-03-26 at 16:25 +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > 6bpc is only legal for RGB and RAW pixel encodings. For the rest
> > > the minimum is 8bpc. Set our lower limit accordingly.
> > 
> > Patch doesn't apply anymore, got a conflict in intel_drv.h. 
> > 
> > 
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c     | 10 +++++++++-
> > >  drivers/gpu/drm/i915/intel_dp_mst.c |  2 +-
> > >  drivers/gpu/drm/i915/intel_drv.h    |  1 +
> > >  3 files changed, 11 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 2aee526ed632..149fdfbcb343 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -2002,6 +2002,14 @@ static int intel_dp_dsc_compute_config(struct
> > > intel_dp
> > > *intel_dp,
> > >  	return 0;
> > >  }
> > >  
> > > +int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state)
> > > +{
> > > +	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
> > > +		return 6 * 3;
> > > +	else
> > > +		return 8 * 3;
> > 
> > Code matches spec, however I think there is a possibility of min_bpp
> > becoming
> > greater than max_bpp. The max_bpc property allows user space to set a value
> > of 6
> > and limits.min_bpp can become 24 because of the code above. Add a check for
> > that
> > in compute_link_config()? Probably would mess up the compute_config() loop
> > too.
> 
> The code looks correct. Ie. should just end up with -EINVAL.
Yup, it does now as I read it carefully again :)
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

However, I don't like the fact we are hiding the detail that min_bpp can be >
max_bpp. If someone decides add a link config optimization starting from
min_bpp, it's easy to miss this detail. 

-DK

> 
> > 
> > 
> > > +}
> > > +
> > >  static int
> > >  intel_dp_compute_link_config(struct intel_encoder *encoder,
> > >  			     struct intel_crtc_state *pipe_config,
> > > @@ -2025,7 +2033,7 @@ intel_dp_compute_link_config(struct intel_encoder
> > > *encoder,
> > >  	limits.min_lane_count = 1;
> > >  	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
> > >  
> > > -	limits.min_bpp = 6 * 3;
> > > +	limits.min_bpp = intel_dp_min_bpp(pipe_config);
> > >  	limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
> > >  
> > >  	if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
> > > diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > b/drivers/gpu/drm/i915/intel_dp_mst.c
> > > index 6d2af7cf48e6..79c229184873 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> > > @@ -119,7 +119,7 @@ static int intel_dp_mst_compute_config(struct
> > > intel_encoder *encoder,
> > >  	limits.min_lane_count =
> > >  	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
> > >  
> > > -	limits.min_bpp = 6 * 3;
> > > +	limits.min_bpp = intel_dp_min_bpp(pipe_config);
> > >  	limits.max_bpp = pipe_config->pipe_bpp;
> > >  
> > >  	intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > b/drivers/gpu/drm/i915/intel_drv.h
> > > index e79954c6271c..13f1b0367287 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -1919,6 +1919,7 @@ void intel_dp_adjust_compliance_config(struct
> > > intel_dp
> > > *intel_dp,
> > >  				       struct link_config_limits *limits);
> > >  bool intel_dp_limited_color_range(const struct intel_crtc_state
> > > *crtc_state,
> > >  				  const struct drm_connector_state *conn_state);
> > > +int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
> > >  bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
> > >  			   i915_reg_t dp_reg, enum port port,
> > >  			   enum pipe *pipe);
> 
> 

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  reply	other threads:[~2019-04-09 21:04 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-26 14:25 [PATCH v2 1/6] drm/i915: Add broadcast RGB property for DP MST Ville Syrjala
2019-03-26 14:25 ` [PATCH v2 2/6] drm/i915: Expose the force_audio property with " Ville Syrjala
2019-03-26 14:25 ` [PATCH v2 3/6] drm/i915: Remove the 8bpc shackles from " Ville Syrjala
2019-03-26 14:25 ` [PATCH v2 4/6] drm/i915: Add max_bpc property for " Ville Syrjala
2019-03-26 14:25 ` [PATCH v2 5/6] drm/i915: Update TRANS_MSA_MISC for fastsets Ville Syrjala
2019-03-26 14:25 ` [PATCH v2 6/6] drm/i915: Set DP min_bpp to 8*3 for non-RGB output formats Ville Syrjala
2019-03-27 14:58   ` Ville Syrjälä
2019-04-09 20:28   ` Dhinakaran Pandiyan
2019-04-09 20:38     ` Ville Syrjälä
2019-04-09 21:04       ` Dhinakaran Pandiyan [this message]
2019-04-11 18:27         ` Ville Syrjälä
2019-04-11 20:33           ` Sripada, Radhakrishna
2019-04-30 17:07             ` Ville Syrjälä
2019-03-26 18:20 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/6] drm/i915: Add broadcast RGB property for DP MST Patchwork
2019-03-26 18:22 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-03-26 18:58 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-27  2:57 ` ✓ Fi.CI.IGT: " Patchwork

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