Re: [PATCH 1/2] drm/i915:bxt: Enable Pooled EU support

[Arun Siluvery <arun.siluvery@linux.intel.com>]

On 17/05/2016 15:34, Daniel Vetter wrote:
> On Thu, May 12, 2016 at 10:37:14AM +0100, Arun Siluvery wrote:
>> This mode allows to assign EUs to pools which can process work collectively.
>> The command to enable this mode should be issued as part of context initialization.
>>
>> The pooled mode is global, once enabled it has to stay the same across all
>> contexts until HW reset hence this is sent in auxiliary golden context batch.
>> Thanks to Mika for the preliminary review and comments.
>>
>> v2: explain why this is enabled in golden context, use feature flag while
>> enabling the support (Chris)
>>
>> v3: Pooled EU support announced in userspace before enabling in kernel,
>> to simplify include all changes in the same patch.
>>
>> User space clients need to know when the pooled EU feature is present
>> and enabled on the hardware so that they can adapt work submissions.
>> Create a new device info flag for this purpose, and create a new GETPARAM
>> entry to allow user space to query its setting.
>>
>> Set has_pooled_eu to true in the Broxton static device info - Broxton
>> supports the feature in hardware and the driver will enable it by
>> default.
>>
>> Opensource users for this feature are mesa, libva and beignet.
>
> Link to those patches would be great. At least I haven't seen anything fly
> by for mesa or libva, might have missed it though. Note that the patches
> must be fully reviewed an ready for merging by respective userspace
> upstream, before we can land the kernel side.

Initially beignet is trying to use it and they are adding support to it. 
I will share links once they send them to the list, reviewed and ready 
to be merged.

regards
Arun

> -Daniel
>
>>
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Winiarski, Michal <michal.winiarski@intel.com>
>> Cc: Zou, Nanhai <nanhai.zou@intel.com>
>> Cc: Yang, Rong R <rong.r.yang@intel.com>
>> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Armin Reese <armin.c.reese@intel.com>
>> Cc: Tim Gore <tim.gore@intel.com>
>> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_dma.c              |  3 +++
>>   drivers/gpu/drm/i915/i915_drv.c              |  1 +
>>   drivers/gpu/drm/i915/i915_drv.h              |  5 ++++-
>>   drivers/gpu/drm/i915/i915_gem_render_state.c | 13 +++++++++++++
>>   drivers/gpu/drm/i915/i915_reg.h              |  2 ++
>>   include/uapi/drm/i915_drm.h                  |  1 +
>>   6 files changed, 24 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
>> index 0eadeb6..5cd2ad4 100644
>> --- a/drivers/gpu/drm/i915/i915_dma.c
>> +++ b/drivers/gpu/drm/i915/i915_dma.c
>> @@ -222,6 +222,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
>>   		if (!value)
>>   			return -ENODEV;
>>   		break;
>> +	case I915_PARAM_HAS_POOLED_EU:
>> +		value = HAS_POOLED_EU(dev);
>> +		break;
>>   	case I915_PARAM_HAS_GPU_RESET:
>>   		value = i915.enable_hangcheck && intel_has_gpu_reset(dev_priv);
>>   		break;
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>> index 5ae7960..33e0fd0 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -357,6 +357,7 @@ static const struct intel_device_info intel_broxton_info = {
>>   	.has_ddi = 1,
>>   	.has_fpga_dbg = 1,
>>   	.has_fbc = 1,
>> +	.has_pooled_eu = 1,
>>   	GEN_DEFAULT_PIPEOFFSETS,
>>   	IVB_CURSOR_OFFSETS,
>>   	BDW_COLORS,
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 7a0b513..5b2a7a3 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -750,7 +750,8 @@ struct intel_csr {
>>   	func(has_llc) sep \
>>   	func(has_snoop) sep \
>>   	func(has_ddi) sep \
>> -	func(has_fpga_dbg)
>> +	func(has_fpga_dbg) sep \
>> +	func(has_pooled_eu)
>>
>>   #define DEFINE_FLAG(name) u8 name:1
>>   #define SEP_SEMICOLON ;
>> @@ -2736,6 +2737,8 @@ struct drm_i915_cmd_table {
>>   				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
>>   				 !IS_BROXTON(dev))
>>
>> +#define HAS_POOLED_EU(dev)	(INTEL_INFO(dev)->has_pooled_eu)
>> +
>>   #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>>   #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
>>   #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
>> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
>> index 7c93327..1284f99 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
>> @@ -94,6 +94,7 @@ free_gem:
>>
>>   static int render_state_setup(struct render_state *so)
>>   {
>> +	struct drm_device *dev = so->obj->base.dev;
>>   	const struct intel_renderstate_rodata *rodata = so->rodata;
>>   	unsigned int i = 0, reloc_index = 0;
>>   	struct page *page;
>> @@ -135,6 +136,18 @@ static int render_state_setup(struct render_state *so)
>>
>>   	so->aux_batch_offset = i * sizeof(u32);
>>
>> +	if (HAS_POOLED_EU(dev)) {
>> +		u32 pool_config = (INTEL_INFO(dev)->subslice_total == 3 ?
>> +				   0x00777000 : 0);
>> +
>> +		OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
>> +		OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
>> +		OUT_BATCH(d, i, pool_config);
>> +		OUT_BATCH(d, i, 0);
>> +		OUT_BATCH(d, i, 0);
>> +		OUT_BATCH(d, i, 0);
>> +	}
>> +
>>   	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
>>   	so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 54ce0b1..dc67e0e 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -442,6 +442,8 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>>    */
>>   #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
>>
>> +#define GEN9_MEDIA_POOL_STATE     ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
>> +#define   GEN9_MEDIA_POOL_ENABLE  (1 << 31)
>>   #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
>>   #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
>>   #define   SC_UPDATE_SCISSOR       (0x1<<1)
>> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
>> index a5524cc..0b0acad 100644
>> --- a/include/uapi/drm/i915_drm.h
>> +++ b/include/uapi/drm/i915_drm.h
>> @@ -357,6 +357,7 @@ typedef struct drm_i915_irq_wait {
>>   #define I915_PARAM_HAS_GPU_RESET	 35
>>   #define I915_PARAM_HAS_RESOURCE_STREAMER 36
>>   #define I915_PARAM_HAS_EXEC_SOFTPIN	 37
>> +#define I915_PARAM_HAS_POOLED_EU	 38
>>
>>   typedef struct drm_i915_getparam {
>>   	__s32 param;
>> --
>> 1.9.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>

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