Re: [PATCH 1/2] drm/i915: Pre-calculate engine context size

[Zhi Wang <zhi.a.wang@intel.com>]

Hi Joonas:
     Can you change GEN8_LR_CONTEXT_RENDER_SIZE = (19 * PAGE_SIZE)? Then we don't need the hack in GVT-g. :P Actually it's 19 pages not 20 pages on BDW.

Thanks,
Zhi.

于 04/26/17 17:11, Joonas Lahtinen 写道:
> Pre-calculate engine context size based on engine class and device
> generation and store it in the engine instance.
>
> Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Oscar Mateo <oscar.mateo@intel.com>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Cc: intel-gvt-dev@lists.freedesktop.org
> ---
>   drivers/gpu/drm/i915/gvt/scheduler.c       |  6 ++--
>   drivers/gpu/drm/i915/i915_guc_submission.c |  3 +-
>   drivers/gpu/drm/i915/intel_engine_cs.c     | 46 +++++++++++++++++++++++++
>   drivers/gpu/drm/i915/intel_lrc.c           | 54 +-----------------------------
>   drivers/gpu/drm/i915/intel_lrc.h           |  2 --
>   drivers/gpu/drm/i915/intel_ringbuffer.h    |  5 +--
>   6 files changed, 53 insertions(+), 63 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
> index a77db23..ac538dc 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -69,8 +69,7 @@ static int populate_shadow_context(struct intel_vgpu_workload *workload)
>   	gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
>   			workload->ctx_desc.lrca);
>   
> -	context_page_num = intel_lr_context_size(
> -			gvt->dev_priv->engine[ring_id]);
> +	context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
>   
>   	context_page_num = context_page_num >> PAGE_SHIFT;
>   
> @@ -333,8 +332,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
>   	gvt_dbg_sched("ring id %d workload lrca %x\n", ring_id,
>   			workload->ctx_desc.lrca);
>   
> -	context_page_num = intel_lr_context_size(
> -			gvt->dev_priv->engine[ring_id]);
> +	context_page_num = gvt->dev_priv->engine[ring_id]->context_size;
>   
>   	context_page_num = context_page_num >> PAGE_SHIFT;
>   
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
> index ab5140b..6c78637 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -1051,8 +1051,7 @@ static int guc_ads_create(struct intel_guc *guc)
>   		dev_priv->engine[RCS]->status_page.ggtt_offset;
>   
>   	for_each_engine(engine, dev_priv, id)
> -		blob->ads.eng_state_size[engine->guc_id] =
> -			intel_lr_context_size(engine);
> +		blob->ads.eng_state_size[engine->guc_id] = engine->context_size;
>   
>   	base = guc_ggtt_offset(vma);
>   	blob->ads.scheduler_policies = base + ptr_offset(blob, policies);
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index 82a274b..091c0c7 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -26,6 +26,10 @@
>   #include "intel_ringbuffer.h"
>   #include "intel_lrc.h"
>   
> +#define GEN9_LR_CONTEXT_RENDER_SIZE	(22 * PAGE_SIZE)
> +#define GEN8_LR_CONTEXT_RENDER_SIZE	(20 * PAGE_SIZE)
> +#define GEN8_LR_CONTEXT_OTHER_SIZE	( 2 * PAGE_SIZE)
> +
>   struct engine_class_info {
>   	const char *name;
>   	int (*init_legacy)(struct intel_engine_cs *engine);
> @@ -107,6 +111,46 @@ static const struct engine_info intel_engines[] = {
>   	},
>   };
>   
> +/**
> + * ___intel_engine_context_size() - return the size of the context for an engine
> + * @dev_priv: i915 device private
> + * @class: engine class
> + *
> + * Each engine class may require a different amount of space for a context
> + * image.
> + *
> + * Return: size (in bytes) of an engine class specific context image
> + *
> + * Note: this size includes the HWSP, which is part of the context image
> + * in LRC mode, but does not include the "shared data page" used with
> + * GuC submission. The caller should account for this if using the GuC.
> + */
> +static u32
> +__intel_engine_context_size(struct drm_i915_private *dev_priv, u8 class)
> +{
> +	WARN_ON(INTEL_GEN(dev_priv) < 8);
> +
> +	switch (class) {
> +	case RENDER_CLASS:
> +		switch (INTEL_GEN(dev_priv)) {
> +		default:
> +			MISSING_CASE(INTEL_GEN(dev_priv));
> +		case 9:
> +			return GEN9_LR_CONTEXT_RENDER_SIZE;
> +		case 8:
> +			return GEN8_LR_CONTEXT_RENDER_SIZE;
> +		}
> +		break;
> +	case VIDEO_DECODE_CLASS:
> +	case VIDEO_ENHANCEMENT_CLASS:
> +	case COPY_ENGINE_CLASS:
> +		return GEN8_LR_CONTEXT_OTHER_SIZE;
> +	}
> +
> +	MISSING_CASE(class);
> +	return GEN8_LR_CONTEXT_OTHER_SIZE;
> +}
> +
>   static int
>   intel_engine_setup(struct drm_i915_private *dev_priv,
>   		   enum intel_engine_id id)
> @@ -134,6 +178,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv,
>   	engine->irq_shift = info->irq_shift;
>   	engine->class = info->class;
>   	engine->instance = info->instance;
> +	engine->context_size = __intel_engine_context_size(dev_priv,
> +							   engine->class);
>   
>   	/* Nothing to do here, execute in order of dependencies */
>   	engine->schedule = NULL;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 5ec064a..0909549 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -138,10 +138,6 @@
>   #include "i915_drv.h"
>   #include "intel_mocs.h"
>   
> -#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
> -#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
> -#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)
> -
>   #define RING_EXECLIST_QFULL		(1 << 0x2)
>   #define RING_EXECLIST1_VALID		(1 << 0x3)
>   #define RING_EXECLIST0_VALID		(1 << 0x4)
> @@ -1918,53 +1914,6 @@ populate_lr_context(struct i915_gem_context *ctx,
>   	return 0;
>   }
>   
> -/**
> - * intel_lr_context_size() - return the size of the context for an engine
> - * @engine: which engine to find the context size for
> - *
> - * Each engine may require a different amount of space for a context image,
> - * so when allocating (or copying) an image, this function can be used to
> - * find the right size for the specific engine.
> - *
> - * Return: size (in bytes) of an engine-specific context image
> - *
> - * Note: this size includes the HWSP, which is part of the context image
> - * in LRC mode, but does not include the "shared data page" used with
> - * GuC submission. The caller should account for this if using the GuC.
> - */
> -uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
> -{
> -	struct drm_i915_private *dev_priv = engine->i915;
> -	int ret;
> -
> -	WARN_ON(INTEL_GEN(dev_priv) < 8);
> -
> -	switch (engine->class) {
> -	case RENDER_CLASS:
> -		switch (INTEL_GEN(dev_priv)) {
> -		default:
> -			MISSING_CASE(INTEL_GEN(dev_priv));
> -		case 9:
> -			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
> -			break;
> -		case 8:
> -			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
> -			break;
> -		}
> -		break;
> -
> -	default:
> -		MISSING_CASE(engine->class);
> -	case VIDEO_DECODE_CLASS:
> -	case VIDEO_ENHANCEMENT_CLASS:
> -	case COPY_ENGINE_CLASS:
> -		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
> -		break;
> -	}
> -
> -	return ret;
> -}
> -
>   static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
>   					    struct intel_engine_cs *engine)
>   {
> @@ -1977,8 +1926,7 @@ static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
>   
>   	WARN_ON(ce->state);
>   
> -	context_size = round_up(intel_lr_context_size(engine),
> -				I915_GTT_PAGE_SIZE);
> +	context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
>   
>   	/* One extra page as the sharing data between driver and GuC */
>   	context_size += PAGE_SIZE * LRC_PPHWSP_PN;
> diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
> index e8015e7..52b3a1f 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/intel_lrc.h
> @@ -78,8 +78,6 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine);
>   struct drm_i915_private;
>   struct i915_gem_context;
>   
> -uint32_t intel_lr_context_size(struct intel_engine_cs *engine);
> -
>   void intel_lr_context_resume(struct drm_i915_private *dev_priv);
>   uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
>   				     struct intel_engine_cs *engine);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index 96710b6..598194d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -196,12 +196,13 @@ struct intel_engine_cs {
>   	enum intel_engine_id id;
>   	unsigned int uabi_id;
>   	unsigned int hw_id;
> +	unsigned int guc_id;
>   
>   	u8 class;
>   	u8 instance;
> +	u32 context_size;
>   
> -	unsigned int guc_id;
> -	u32		mmio_base;
> +	u32 mmio_base;
>   	unsigned int irq_shift;
>   	struct intel_ring *buffer;
>   	struct intel_timeline *timeline;

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx