Re: [Intel-gfx] [PATCH 1/2] drm/i915/dp: Optimize the FRL configuration for HDMI2.1 PCON

["Shankar, Uma" <uma.shankar@intel.com>]

> -----Original Message-----
> From: Nautiyal, Ankit K <ankit.k.nautiyal@intel.com>
> Sent: Friday, October 29, 2021 11:32 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Sharma, Swati2 <swati2.sharma@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>
> Subject: [PATCH 1/2] drm/i915/dp: Optimize the FRL configuration for HDMI2.1
> PCON
> 
> Currently the HDMI2.1 PCON's frl link config DPCD registers are reset and configured
> even if they are already configured.
> Also the HDMI Link Mode does not settle to FRL MODE immediately after HDMI Link
> Status is active.
> 
> This patch:
> -Checks if the PCON is already configured for FRL.
> -Include HDMI Link Mode in wait for loop along with HDMI Link status DPCD.

Looks good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 37 +++++++++++++++----------
>  1 file changed, 23 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6d5988f0f067..f5fd106e555c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2198,6 +2198,18 @@ static int intel_dp_hdmi_sink_max_frl(struct intel_dp
> *intel_dp)
>  	return max_frl_rate;
>  }
> 
> +static bool
> +intel_dp_pcon_is_frl_trained(struct intel_dp *intel_dp,
> +			     u8 max_frl_bw_mask, u8 *frl_trained_mask) {
> +	if (drm_dp_pcon_hdmi_link_active(&intel_dp->aux) &&
> +	    drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, frl_trained_mask) ==
> DP_PCON_HDMI_MODE_FRL &&
> +	    *frl_trained_mask >= max_frl_bw_mask)
> +		return true;
> +
> +	return false;
> +}
> +
>  static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)  {  #define
> TIMEOUT_FRL_READY_MS 500 @@ -2208,10 +2220,6 @@ static int
> intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)
>  	u8 max_frl_bw_mask = 0, frl_trained_mask;
>  	bool is_active;
> 
> -	ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux);
> -	if (ret < 0)
> -		return ret;
> -
>  	max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;
>  	drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw);
> 
> @@ -2223,6 +2231,12 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp
> *intel_dp)
>  	if (max_frl_bw <= 0)
>  		return -EINVAL;
> 
> +	max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
> +	drm_dbg(&i915->drm, "MAX_FRL_BW_MASK = %u\n", max_frl_bw_mask);
> +
> +	if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask,
> &frl_trained_mask))
> +		goto frl_trained;
> +
>  	ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false);
>  	if (ret < 0)
>  		return ret;
> @@ -2232,7 +2246,6 @@ static int intel_dp_pcon_start_frl_training(struct intel_dp
> *intel_dp)
>  	if (!is_active)
>  		return -ETIMEDOUT;
> 
> -	max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);
>  	ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw,
>  					  DP_PCON_ENABLE_SEQUENTIAL_LINK);
>  	if (ret < 0)
> @@ -2248,19 +2261,15 @@ static int intel_dp_pcon_start_frl_training(struct
> intel_dp *intel_dp)
>  	 * Wait for FRL to be completed
>  	 * Check if the HDMI Link is up and active.
>  	 */
> -	wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) ==
> true, TIMEOUT_HDMI_LINK_ACTIVE_MS);
> +	wait_for(is_active =
> +		 intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask,
> &frl_trained_mask),
> +		 TIMEOUT_HDMI_LINK_ACTIVE_MS);
> 
>  	if (!is_active)
>  		return -ETIMEDOUT;
> 
> -	/* Verify HDMI Link configuration shows FRL Mode */
> -	if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) !=
> -	    DP_PCON_HDMI_MODE_FRL) {
> -		drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n");
> -		return -EINVAL;
> -	}
> -	drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK =
> %u\n", max_frl_bw_mask, frl_trained_mask);
> -
> +frl_trained:
> +	drm_dbg(&i915->drm, "FRL_TRAINED_MASK = %u\n", frl_trained_mask);
>  	intel_dp->frl.trained_rate_gbps =
> intel_dp_pcon_get_frl_mask(frl_trained_mask);
>  	intel_dp->frl.is_trained = true;
>  	drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp-
> >frl.trained_rate_gbps);
> --
> 2.25.1