Re: [PATCH v2 07/15] drm/i915: Fix PTE decode during initial plane readout

[Andrzej Hajda <andrzej.hajda@intel.com>]

On 15.12.2023 11:59, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> When multiple pipes are enabled by the BIOS we try to read out each
> in turn. But we do the readout for the second only after the inherited
> vma for the first has been rebound into its original place (and thus
> the PTEs have been rewritten). Unlike the BIOS we set some high caching
> bits in the PTE on MTL which confuses the readout for the second plane.
> Filter out the non-address bits from the PTE value appropriately to
> fix this.
> 
> I suppose it might also be possible that the BIOS would already set
> some caching bits as well, in which case we'd run into this same
> issue already for the first plane.
> 
> TODO:
> - should abstract the PTE decoding to avoid details leaking all over
> - should probably do the readout for all the planes before
>    we touch anything (including the PTEs) so that we truly read
>    out the BIOS state
> 
> Cc: Paz Zcharya <pazz@chromium.org>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Helper can be useful (but I guess not many users atm).
The change looks correct anyway.

Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>

Regards
Andrzej


> ---
>   drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> index a55c09cbd0e4..ffc92b18fcf5 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c
> @@ -72,7 +72,7 @@ initial_plane_vma(struct drm_i915_private *i915,
>   			return NULL;
>   		}
>   
> -		phys_base = pte & I915_GTT_PAGE_MASK;
> +		phys_base = pte & GEN12_GGTT_PTE_ADDR_MASK;
>   		mem = i915->mm.regions[INTEL_REGION_LMEM_0];
>   
>   		/*