From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>,
<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH v15 1/9] gpu/drm/i915: Update indentation for VRR registers and bits
Date: Mon, 10 Jun 2024 09:49:10 +0530 [thread overview]
Message-ID: <5d18fd7e-492e-4ece-bee2-1643556514ca@intel.com> (raw)
In-Reply-To: <20240610024825.823096-2-mitulkumar.ajitkumar.golani@intel.com>
Subject: drm/i915 should suffice.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
On 6/10/2024 8:18 AM, Mitul Golani wrote:
> Update the indentation for the VRR register definition and
> its bits, and fix checkpatch issues to ensure smooth movement
> of registers and bits.
>
> --v2:
> - Keep XELPD_VRR_CTL_VRR_GUARDBAND(x) to avoid readability (Ankit).
> - Fix all indentation related VRR registers and bits instead of
> checkpatch one.
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 174 ++++++++++++++++----------------
> 1 file changed, 87 insertions(+), 87 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7daf902772e4..a10591424338 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1148,104 +1148,104 @@
> #define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
>
> /* VRR registers */
> -#define _TRANS_VRR_CTL_A 0x60420
> -#define _TRANS_VRR_CTL_B 0x61420
> -#define _TRANS_VRR_CTL_C 0x62420
> -#define _TRANS_VRR_CTL_D 0x63420
> -#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
> -#define VRR_CTL_VRR_ENABLE REG_BIT(31)
> -#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
> -#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
> -#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
> -#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
> -#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
> -#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
> -#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
> -
> -#define _TRANS_VRR_VMAX_A 0x60424
> -#define _TRANS_VRR_VMAX_B 0x61424
> -#define _TRANS_VRR_VMAX_C 0x62424
> -#define _TRANS_VRR_VMAX_D 0x63424
> +#define _TRANS_VRR_CTL_A 0x60420
> +#define _TRANS_VRR_CTL_B 0x61420
> +#define _TRANS_VRR_CTL_C 0x62420
> +#define _TRANS_VRR_CTL_D 0x63420
> +#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
> +#define VRR_CTL_VRR_ENABLE REG_BIT(31)
> +#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30)
> +#define VRR_CTL_FLIP_LINE_EN REG_BIT(29)
> +#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
> +#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
> +#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
> +#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
> +#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
> +
> +#define _TRANS_VRR_VMAX_A 0x60424
> +#define _TRANS_VRR_VMAX_B 0x61424
> +#define _TRANS_VRR_VMAX_C 0x62424
> +#define _TRANS_VRR_VMAX_D 0x63424
> #define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
> -#define VRR_VMAX_MASK REG_GENMASK(19, 0)
> +#define VRR_VMAX_MASK REG_GENMASK(19, 0)
>
> -#define _TRANS_VRR_VMIN_A 0x60434
> -#define _TRANS_VRR_VMIN_B 0x61434
> -#define _TRANS_VRR_VMIN_C 0x62434
> -#define _TRANS_VRR_VMIN_D 0x63434
> +#define _TRANS_VRR_VMIN_A 0x60434
> +#define _TRANS_VRR_VMIN_B 0x61434
> +#define _TRANS_VRR_VMIN_C 0x62434
> +#define _TRANS_VRR_VMIN_D 0x63434
> #define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
> -#define VRR_VMIN_MASK REG_GENMASK(15, 0)
> +#define VRR_VMIN_MASK REG_GENMASK(15, 0)
>
> -#define _TRANS_VRR_VMAXSHIFT_A 0x60428
> -#define _TRANS_VRR_VMAXSHIFT_B 0x61428
> -#define _TRANS_VRR_VMAXSHIFT_C 0x62428
> -#define _TRANS_VRR_VMAXSHIFT_D 0x63428
> +#define _TRANS_VRR_VMAXSHIFT_A 0x60428
> +#define _TRANS_VRR_VMAXSHIFT_B 0x61428
> +#define _TRANS_VRR_VMAXSHIFT_C 0x62428
> +#define _TRANS_VRR_VMAXSHIFT_D 0x63428
> #define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
> - _TRANS_VRR_VMAXSHIFT_A)
> -#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
> -#define VRR_VMAXSHIFT_DEC REG_BIT(16)
> -#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
> -
> -#define _TRANS_VRR_STATUS_A 0x6042C
> -#define _TRANS_VRR_STATUS_B 0x6142C
> -#define _TRANS_VRR_STATUS_C 0x6242C
> -#define _TRANS_VRR_STATUS_D 0x6342C
> -#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
> -#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
> -#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
> -#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
> -#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
> -#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
> -#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
> -#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
> -#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
> -#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
> -#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
> -#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
> -#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
> -#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
> -#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
> -
> -#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
> -#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
> -#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
> -#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
> + _TRANS_VRR_VMAXSHIFT_A)
> +#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16)
> +#define VRR_VMAXSHIFT_DEC REG_BIT(16)
> +#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0)
> +
> +#define _TRANS_VRR_STATUS_A 0x6042c
> +#define _TRANS_VRR_STATUS_B 0x6142c
> +#define _TRANS_VRR_STATUS_C 0x6242c
> +#define _TRANS_VRR_STATUS_D 0x6342c
> +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
> +#define VRR_STATUS_VMAX_REACHED REG_BIT(31)
> +#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30)
> +#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29)
> +#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28)
> +#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27)
> +#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26)
> +#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20)
> +#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
> +#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
> +#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
> +#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
> +#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
> +#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
> +#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
> +
> +#define _TRANS_VRR_VTOTAL_PREV_A 0x60480
> +#define _TRANS_VRR_VTOTAL_PREV_B 0x61480
> +#define _TRANS_VRR_VTOTAL_PREV_C 0x62480
> +#define _TRANS_VRR_VTOTAL_PREV_D 0x63480
> #define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
> - _TRANS_VRR_VTOTAL_PREV_A)
> -#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
> -#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
> -#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
> -#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
> -
> -#define _TRANS_VRR_FLIPLINE_A 0x60438
> -#define _TRANS_VRR_FLIPLINE_B 0x61438
> -#define _TRANS_VRR_FLIPLINE_C 0x62438
> -#define _TRANS_VRR_FLIPLINE_D 0x63438
> + _TRANS_VRR_VTOTAL_PREV_A)
> +#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31)
> +#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30)
> +#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29)
> +#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0)
> +
> +#define _TRANS_VRR_FLIPLINE_A 0x60438
> +#define _TRANS_VRR_FLIPLINE_B 0x61438
> +#define _TRANS_VRR_FLIPLINE_C 0x62438
> +#define _TRANS_VRR_FLIPLINE_D 0x63438
> #define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \
> - _TRANS_VRR_FLIPLINE_A)
> -#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
> + _TRANS_VRR_FLIPLINE_A)
> +#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0)
>
> -#define _TRANS_VRR_STATUS2_A 0x6043C
> -#define _TRANS_VRR_STATUS2_B 0x6143C
> -#define _TRANS_VRR_STATUS2_C 0x6243C
> -#define _TRANS_VRR_STATUS2_D 0x6343C
> +#define _TRANS_VRR_STATUS2_A 0x6043c
> +#define _TRANS_VRR_STATUS2_B 0x6143c
> +#define _TRANS_VRR_STATUS2_C 0x6243c
> +#define _TRANS_VRR_STATUS2_D 0x6343c
> #define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
> -#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
> +#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0)
>
> -#define _TRANS_PUSH_A 0x60A70
> -#define _TRANS_PUSH_B 0x61A70
> -#define _TRANS_PUSH_C 0x62A70
> -#define _TRANS_PUSH_D 0x63A70
> +#define _TRANS_PUSH_A 0x60a70
> +#define _TRANS_PUSH_B 0x61a70
> +#define _TRANS_PUSH_C 0x62a70
> +#define _TRANS_PUSH_D 0x63a70
> #define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)
> -#define TRANS_PUSH_EN REG_BIT(31)
> -#define TRANS_PUSH_SEND REG_BIT(30)
> -
> -#define _TRANS_VRR_VSYNC_A 0x60078
> -#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
> -#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
> -#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
> -#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
> -#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
> +#define TRANS_PUSH_EN REG_BIT(31)
> +#define TRANS_PUSH_SEND REG_BIT(30)
> +
> +#define _TRANS_VRR_VSYNC_A 0x60078
> +#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
> +#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16)
> +#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
> +#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0)
> +#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
>
> /* VGA port control */
> #define ADPA _MMIO(0x61100)
next prev parent reply other threads:[~2024-06-10 4:19 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-10 2:48 [PATCH v15 0/9] Implement CMRR Support Mitul Golani
2024-06-10 2:48 ` [PATCH v15 1/9] gpu/drm/i915: Update indentation for VRR registers and bits Mitul Golani
2024-06-10 4:19 ` Nautiyal, Ankit K [this message]
2024-06-10 2:48 ` [PATCH v15 2/9] drm/i915: Separate VRR related register definitions Mitul Golani
2024-06-10 4:46 ` Nautiyal, Ankit K
2024-06-10 2:48 ` [PATCH v15 3/9] drm/i915: Define and compute Transcoder CMRR registers Mitul Golani
2024-06-10 2:48 ` [PATCH v15 4/9] drm/i915: Update trans_vrr_ctl flag when cmrr is computed Mitul Golani
2024-06-10 2:48 ` [PATCH v15 5/9] drm/dp: Add refresh rate divider to struct representing AS SDP Mitul Golani
2024-06-10 2:48 ` [PATCH v15 6/9] drm/i915/display: Add support for pack and unpack Mitul Golani
2024-06-10 2:48 ` [PATCH v15 7/9] drm/i915/display: Compute Adaptive sync SDP params Mitul Golani
2024-06-10 2:48 ` [PATCH v15 8/9] drm/i915/display: Compute vrr vsync params Mitul Golani
2024-06-10 2:48 ` [PATCH v15 9/9] drm/i915: Compute CMRR and calculate vtotal Mitul Golani
2024-06-10 3:25 ` ✗ Fi.CI.CHECKPATCH: warning for Implement CMRR Support (rev16) Patchwork
2024-06-10 3:25 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-06-10 3:31 ` ✓ Fi.CI.BAT: success " Patchwork
2024-06-10 4:53 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-06-11 4:34 ` [PATCH v15 0/9] Implement CMRR Support Kandpal, Suraj
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