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From: "Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>
To: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "dri-devel@lists.freedesktop.org" <dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/guc: add the GSC CS to the GuC capture list
Date: Wed, 16 Nov 2022 17:26:16 +0000	[thread overview]
Message-ID: <5d305b68f98ca7fc3c78b02bf3f53af93848db5a.camel@intel.com> (raw)
In-Reply-To: <20221111001832.4144910-1-daniele.ceraolospurio@intel.com>

I'm assuming that you have verified that the GuC ADS code is calling for the registration of the GSC capture register
list accordingly and for the correct tile. That said:

Reviewed-by: Alan Previn <alan.previn.teres.alexis@intel.com>

On Thu, 2022-11-10 at 16:18 -0800, Ceraolo Spurio, Daniele wrote:
> For the GSC engine we only want to capture the instance regs.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> index 4e6dca707d94..1d49a7ec0bd8 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_capture.c
> @@ -132,6 +132,11 @@ static const struct __guc_mmio_reg_descr xe_lpd_blt_inst_regs[] = {
>  	COMMON_BASE_ENGINE_INSTANCE,
>  };
>  
> +/* XE_LPD - GSC Per-Engine-Instance */
> +static const struct __guc_mmio_reg_descr xe_lpd_gsc_inst_regs[] = {
> +	COMMON_BASE_ENGINE_INSTANCE,
> +};
> +
>  /* GEN9 - Global */
>  static const struct __guc_mmio_reg_descr default_global_regs[] = {
>  	COMMON_BASE_GLOBAL,
> @@ -177,6 +182,8 @@ static struct __guc_mmio_reg_descr_group default_lists[] = {
>  	MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS),
>  	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS),
>  	MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS),
> +	MAKE_REGLIST(xe_lpd_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS),
>  	{}
>  };
>  
> @@ -192,6 +199,8 @@ static const struct __guc_mmio_reg_descr_group xe_lpd_lists[] = {
>  	MAKE_REGLIST(xe_lpd_vec_inst_regs, PF, ENGINE_INSTANCE, GUC_VIDEOENHANCE_CLASS),
>  	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_BLITTER_CLASS),
>  	MAKE_REGLIST(xe_lpd_blt_inst_regs, PF, ENGINE_INSTANCE, GUC_BLITTER_CLASS),
> +	MAKE_REGLIST(empty_regs_list, PF, ENGINE_CLASS, GUC_GSC_OTHER_CLASS),
> +	MAKE_REGLIST(xe_lpd_gsc_inst_regs, PF, ENGINE_INSTANCE, GUC_GSC_OTHER_CLASS),
>  	{}
>  };
>  
> @@ -454,6 +463,8 @@ __stringify_engclass(u32 class)
>  		return "Blitter";
>  	case GUC_COMPUTE_CLASS:
>  		return "Compute";
> +	case GUC_GSC_OTHER_CLASS:
> +		return "GSC-Other";
>  	default:
>  		break;
>  	}
> -- 
> 2.37.3
> 


      parent reply	other threads:[~2022-11-16 17:26 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-11  0:18 [Intel-gfx] [PATCH] drm/i915/guc: add the GSC CS to the GuC capture list Daniele Ceraolo Spurio
2022-11-11  5:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-11-11 23:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-11-16 17:26 ` Teres Alexis, Alan Previn [this message]

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