Re: [PATCH v2 3/3] drm/i915/perf: enable OAR context save/restore of performance counters

[Lionel Landwerlin <lionel.g.landwerlin@intel.com>]

On 17/10/2019 10:20, Umesh Nerlige Ramappa wrote:
> From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>


Also put yourself as the author ;)


And finally put that patch before the other so that we once perf support 
is enabled, all the features are there.


Cheers,

-Lionel


>
> We want this so we can preempt performance queries and keep the system
> responsive even when long running queries are ongoing. We avoid doing
> it for all contexts.
>
> v2: use LRI to modify context control (Chris)
> v3: use MASKED_FIELD to program just the masked bits (Chris)
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
> ---
>   drivers/gpu/drm/i915/gt/intel_lrc.h |  1 +
>   drivers/gpu/drm/i915/i915_perf.c    | 39 +++++++++++++++++++++++++++++
>   2 files changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.h b/drivers/gpu/drm/i915/gt/intel_lrc.h
> index 99dc576a4e25..b6daac712c9e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.h
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.h
> @@ -43,6 +43,7 @@ struct intel_engine_cs;
>   #define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)
>   #define   CTX_CTRL_RS_CTX_ENABLE		(1 << 1)
>   #define	  CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT	(1 << 2)
> +#define	  GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE	(1 << 8)
>   #define RING_CONTEXT_STATUS_PTR(base)		_MMIO((base) + 0x3a0)
>   #define RING_EXECLIST_SQ_CONTENTS(base)		_MMIO((base) + 0x510)
>   #define RING_EXECLIST_CONTROL(base)		_MMIO((base) + 0x550)
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index abc2b7a6dc92..47a8d610af6e 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -2211,6 +2211,36 @@ static int gen8_configure_context(struct i915_gem_context *ctx,
>   	return err;
>   }
>   
> +static int gen12_emit_oar_config(struct intel_context *ce, bool enable)
> +{
> +	struct i915_request *rq;
> +	u32 *cs;
> +	int err = 0;
> +
> +	rq = i915_request_create(ce);
> +	if (IS_ERR(rq))
> +		return PTR_ERR(rq);
> +
> +	cs = intel_ring_begin(rq, 4);
> +	if (IS_ERR(cs)) {
> +		err = PTR_ERR(cs);
> +		goto out;
> +	}
> +
> +	*cs++ = MI_LOAD_REGISTER_IMM(1);
> +	*cs++ = i915_mmio_reg_offset(RING_CONTEXT_CONTROL(ce->engine->mmio_base));
> +	*cs++ = _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
> +			      enable ? GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE : 0);
> +	*cs++ = MI_NOOP;
> +
> +	intel_ring_advance(rq, cs);
> +
> +out:
> +	i915_request_add(rq);
> +
> +	return err;
> +}
> +
>   /*
>    * Manages updating the per-context aspects of the OA stream
>    * configuration across all contexts.
> @@ -2425,6 +2455,15 @@ static int gen12_enable_metric_set(struct i915_perf_stream *stream)
>   	if (ret)
>   		return ret;
>   
> +	/*
> +	 * For Gen12, performance counters are context
> +	 * saved/restored. Only enable it for the context that
> +	 * requested this.
> +	 */
> +	ret = gen12_emit_oar_config(stream->pinned_ctx, oa_config != NULL);
> +	if (ret)
> +		return ret;
> +
>   	return emit_oa_config(stream, oa_context(stream));
>   }
>   


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