Re: [PATCH 1/2] drm/i915: Stop overwriting RING_IMR in rcs resume

[Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>]

On 18/04/2019 14:27, Chris Wilson wrote:
> We store the engine->imr mask and set up the RING_IMR register on
> restarting the engine. We do not then want to overwrite it with
> an incomplete mask later as we may then lose interrupts!
> 
> Reported-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ---
>   1 file changed, 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 029fd8ec1857..00bd9eeb053d 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -873,9 +873,6 @@ static int init_render_ring(struct intel_engine_cs *engine)
>   	if (IS_GEN_RANGE(dev_priv, 6, 7))
>   		I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
>   
> -	if (INTEL_GEN(dev_priv) >= 6)
> -		ENGINE_WRITE(engine, RING_IMR, ~engine->irq_keep_mask);
> -
>   	return 0;
>   }
>   
> 

Is it perhaps a way to enable L3_DPF on IVB and HSW when breadcrumbs are 
off (no one listening)? Mind you, the same should be done in this case 
under execlists for ctx switch irq. I just can't find the code there 
which unmasks it unless a single engine->irq_enable/irq_disable cycle is 
guaranteed on load indirectly. Is there a request_wait or wait_for_idle 
hidden somewhere during init? Or I missed the ball completely?

Regards,

Tvrtko
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