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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 31/32] drm/i915/execlists: Virtual engine bonding
Date: Thu, 18 Apr 2019 11:24:40 +0100	[thread overview]
Message-ID: <673d2d50-ae0a-428b-eaa0-71719e0aede1@linux.intel.com> (raw)
In-Reply-To: <155558156269.4314.1903788784014193441@skylake-alporthouse-com>


On 18/04/2019 10:59, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-04-18 10:50:30)
>>
>> On 18/04/2019 10:13, Chris Wilson wrote:
>>> Quoting Tvrtko Ursulin (2019-04-18 09:57:43)
>>>>
>>>> On 18/04/2019 07:57, Chris Wilson wrote:
>>>>> Quoting Tvrtko Ursulin (2019-04-18 07:47:51)
>>>>>>
>>>>>> On 17/04/2019 08:56, Chris Wilson wrote:
>>>>>>> +static void
>>>>>>> +virtual_bond_execute(struct i915_request *rq, struct dma_fence *signal)
>>>>>>> +{
>>>>>>> +     struct virtual_engine *ve = to_virtual_engine(rq->engine);
>>>>>>> +     struct ve_bond *bond;
>>>>>>> +
>>>>>>> +     bond = virtual_find_bond(ve, to_request(signal)->engine);
>>>>>>> +     if (bond) {
>>>>>>> +             intel_engine_mask_t old, new, cmp;
>>>>>>> +
>>>>>>> +             cmp = READ_ONCE(rq->execution_mask);
>>>>>>> +             do {
>>>>>>> +                     old = cmp;
>>>>>>> +                     new = cmp & bond->sibling_mask;
>>>>>>> +             } while ((cmp = cmpxchg(&rq->execution_mask, old, new)) != old);
>>>>>>
>>>>>> Loop implies someone else might be modifying the rq->execution_mask in
>>>>>> parallel?
>>>>>
>>>>> There's nothing that prevents there being multiple bonds being
>>>>> executed simultaneously (other than practicality). There's also nothing
>>>>> that says this should be the only way to modify rq->execution_mask in
>>>>> the future.
>>>>
>>>> But request is one, how can it be submitted multiple times simultaneously?
>>>
>>> You mean "How can it be signaled multiple times simultaneously?"
>>
>> Okay yes, signaled. You could give same submit fence to multiple slaves,
>> but you can't have same slave request receive notification from multiple
>> masters.
>>
>> Or you can if you build a composite fence and pass that in? Is this the
>> story about signal-on-any vs signal-on-all?
> 
> There's nothing inherent in the design to prevent virtual_bond_execute
> being called multiple times given multiple fences along one or more
> engines.
> 
> There's a practical limitation in the proposed uAPI to limit it to a
> single submit-fence, but may indeed be a composite fence. There's also
> the question of whether to squeeze in syncobj support.

Ok. Just drop in a comment with the loop please.

>>>>>>> +
>>>>>>> +     err = check_user_mbz(&ext->flags);
>>>>>>> +     if (err)
>>>>>>> +             return err;
>>>>>>> +
>>>>>>> +     for (n = 0; n < ARRAY_SIZE(ext->mbz64); n++) {
>>>>>>> +             err = check_user_mbz(&ext->mbz64[n]);
>>>>>>> +             if (err)
>>>>>>> +                     return err;
>>>>>>> +     }
>>>>>>> +
>>>>>>> +     if (get_user(class, &ext->master_class))
>>>>>>> +             return -EFAULT;
>>>>>>> +
>>>>>>> +     if (get_user(instance, &ext->master_instance))
>>>>>>> +             return -EFAULT;
>>>>>>> +
>>>>>>> +     master = intel_engine_lookup_user(set->ctx->i915, class, instance);
>>>>>>> +     if (!master) {
>>>>>>> +             DRM_DEBUG("Unrecognised master engine: { class:%d, instance:%d }\n",
>>>>>>> +                       class, instance);
>>>>>>> +             return -EINVAL;
>>>>>>> +     }
>>>>>>> +
>>>>>>> +     if (get_user(num_bonds, &ext->num_bonds))
>>>>>>> +             return -EFAULT;
>>>>>>
>>>>>> Should num_bonds > virtual->num_siblings be an error?
>>>>>
>>>>> They could specify the same bond multiple times for whatever reason (and
>>>>> probably should allow skipping NONE?), if the target doesn't exist that's
>>>>> definitely an error.
>>>>
>>>> So which bond we pick if they specify multiple ones? Just the first one
>>>> found. Hm actually I was thinking about making sure each master is only
>>>> specified once, not siblings. For siblings we indeed do not care.
>>>
>>> No, it's a mask of if parent executes on master, use this set of
>>> children.
>>>
>>> I was reasonably happy to use a cumulative mask if master is specified
>>> by more than one bond ext; but maybe it should be an intersection. Hmm.
>>
>> Do you see a realistic and making sense use case for specifying the same
>> master in multiple bonds? If not I'd just disallow it and then we don't
>> have a question of union vs intersection policy.
> 
> Rather the opposite, I don't see that it breaks anything nor need it be
> ill-defined, hence no reason to reject as a means to protect oneself.

I don't mean it's dangerous or poorly defined. In that sense your 
current implementation of using an union is fine. (Earlier I forgot that 
you skip creating multiple bond objects in this case.)

Regards,

Tvrtko
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  reply	other threads:[~2019-04-18 10:24 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-17  7:56 [PATCH 01/32] drm/i915: Seal races between async GPU cancellation, retirement and signaling Chris Wilson
2019-04-17  7:56 ` [PATCH 02/32] drm/i915: Verify workarounds immediately after application Chris Wilson
2019-04-17  7:56 ` [PATCH 03/32] drm/i915: Verify the engine workarounds stick on application Chris Wilson
2019-04-17  7:56 ` [PATCH 04/32] drm/i915: Make workaround verification *optional* Chris Wilson
2019-04-17  9:37   ` Tvrtko Ursulin
2019-04-17  7:56 ` [PATCH 05/32] drm/i915/selftests: Verify whitelist of context registers Chris Wilson
2019-04-17  7:56 ` [PATCH 06/32] drm/i915: Store the default sseu setup on the engine Chris Wilson
2019-04-17  9:40   ` Tvrtko Ursulin
2019-04-24  9:45     ` Chris Wilson
2019-04-17  7:56 ` [PATCH 07/32] drm/i915: Move GraphicsTechnology files under gt/ Chris Wilson
2019-04-17  9:42   ` Tvrtko Ursulin
2019-04-18 12:04   ` Joonas Lahtinen
2019-04-23  8:57     ` Joonas Lahtinen
2019-04-23  9:40       ` Jani Nikula
2019-04-23 16:46         ` Rodrigo Vivi
2019-04-17  7:56 ` [PATCH 08/32] drm/i915: Introduce struct intel_wakeref Chris Wilson
2019-04-17  9:45   ` Tvrtko Ursulin
2019-04-17  7:56 ` [PATCH 09/32] drm/i915: Pull the GEM powermangement coupling into its own file Chris Wilson
2019-04-17  7:56 ` [PATCH 10/32] drm/i915: Introduce context->enter() and context->exit() Chris Wilson
2019-04-17  7:56 ` [PATCH 11/32] drm/i915: Pass intel_context to i915_request_create() Chris Wilson
2019-04-17  7:56 ` [PATCH 12/32] drm/i915: Invert the GEM wakeref hierarchy Chris Wilson
2019-04-18 12:42   ` Tvrtko Ursulin
2019-04-18 13:07     ` Chris Wilson
2019-04-18 13:22       ` Chris Wilson
2019-04-23 13:02   ` Tvrtko Ursulin
2019-04-17  7:56 ` [PATCH 13/32] drm/i915/gvt: Pin the per-engine GVT shadow contexts Chris Wilson
2019-04-17  7:56 ` [PATCH 14/32] drm/i915: Explicitly pin the logical context for execbuf Chris Wilson
2019-04-17  7:56 ` [PATCH 15/32] drm/i915: Export intel_context_instance() Chris Wilson
2019-04-17  7:56 ` [PATCH 16/32] drm/i915/selftests: Use the real kernel context for sseu isolation tests Chris Wilson
2019-04-17  7:56 ` [PATCH 17/32] drm/i915/selftests: Pass around intel_context for sseu Chris Wilson
2019-04-17  7:56 ` [PATCH 18/32] drm/i915: Pass intel_context to intel_context_pin_lock() Chris Wilson
2019-04-17  7:56 ` [PATCH 19/32] drm/i915: Split engine setup/init into two phases Chris Wilson
2019-04-17  7:56 ` [PATCH 20/32] drm/i915: Switch back to an array of logical per-engine HW contexts Chris Wilson
2019-04-17  7:56 ` [PATCH 21/32] drm/i915: Remove intel_context.active_link Chris Wilson
2019-04-17  9:47   ` Tvrtko Ursulin
2019-04-17  7:56 ` [PATCH 22/32] drm/i915: Move i915_request_alloc into selftests/ Chris Wilson
2019-04-17  7:56 ` [PATCH 23/32] drm/i915: Allow multiple user handles to the same VM Chris Wilson
2019-04-17  7:56 ` [PATCH 24/32] drm/i915: Restore control over ppgtt for context creation ABI Chris Wilson
2019-04-17  7:56 ` [PATCH 25/32] drm/i915: Allow a context to define its set of engines Chris Wilson
2019-04-17  9:50   ` Tvrtko Ursulin
2019-04-17  7:56 ` [PATCH 26/32] drm/i915: Re-expose SINGLE_TIMELINE flags for context creation Chris Wilson
2019-04-17  7:56 ` [PATCH 27/32] drm/i915: Allow userspace to clone contexts on creation Chris Wilson
2019-04-17  9:50   ` Tvrtko Ursulin
2019-04-17  7:56 ` [PATCH 28/32] drm/i915: Load balancing across a virtual engine Chris Wilson
2019-04-17 11:26   ` Tvrtko Ursulin
2019-04-17 13:51     ` Chris Wilson
2019-04-17  7:56 ` [PATCH 29/32] drm/i915: Apply an execution_mask to the virtual_engine Chris Wilson
2019-04-17 11:43   ` Tvrtko Ursulin
2019-04-17 11:57     ` Chris Wilson
2019-04-17 12:35       ` Tvrtko Ursulin
2019-04-17 12:46         ` Chris Wilson
2019-04-17 13:32           ` Tvrtko Ursulin
2019-04-18  7:24             ` Chris Wilson
2019-04-17  7:56 ` [PATCH 30/32] drm/i915: Extend execution fence to support a callback Chris Wilson
2019-04-17  7:56 ` [PATCH 31/32] drm/i915/execlists: Virtual engine bonding Chris Wilson
2019-04-18  6:47   ` Tvrtko Ursulin
2019-04-18  6:57     ` Chris Wilson
2019-04-18  8:57       ` Tvrtko Ursulin
2019-04-18  9:13         ` Chris Wilson
2019-04-18  9:50           ` Tvrtko Ursulin
2019-04-18  9:59             ` Chris Wilson
2019-04-18 10:24               ` Tvrtko Ursulin [this message]
2019-04-17  7:56 ` [PATCH 32/32] drm/i915: Allow specification of parallel execbuf Chris Wilson
2019-04-17  8:46 ` [PATCH 01/32] drm/i915: Seal races between async GPU cancellation, retirement and signaling Chris Wilson
2019-04-17 11:33 ` ✗ Fi.CI.BAT: failure for series starting with [01/32] " Patchwork
2019-04-18 10:32 ` [PATCH 01/32] " Tvrtko Ursulin
2019-04-18 10:40   ` Chris Wilson
2019-04-23 12:59 ` Tvrtko Ursulin

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