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From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Andrzej Hajda <andrzej.hajda@intel.com>,
	Intel-gfx@lists.freedesktop.org,
	 dri-devel@lists.freedesktop.org
Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Subject: Re: [Intel-gfx] [PATCH v3] drm/i915: Do not cover all future platforms in TLB invalidation
Date: Tue, 10 Jan 2023 09:16:12 +0000	[thread overview]
Message-ID: <6a861c63-39b7-e5e2-b7c5-43cf9b7130f8@linux.intel.com> (raw)
In-Reply-To: <ba227180-066a-8e07-9df6-a9d4e6ec2a05@intel.com>


On 10/01/2023 08:23, Andrzej Hajda wrote:
> 
> 
> On 09.01.2023 13:24, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Revert to the original explicit approach and document the reasoning
>> behind it.
>>
>> v2:
>>   * DG2 needs to be covered too. (Matt)
>>
>> v3:
>>   * Full version check for Gen12 to avoid catching all future platforms.
>>     (Matt)
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
>> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
>> Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com> # v1
>> ---
>>   drivers/gpu/drm/i915/gt/intel_gt.c | 17 +++++++++++++++--
>>   1 file changed, 15 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c 
>> b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index 7eeee5a7cb33..5521fa057aab 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -1070,10 +1070,23 @@ static void mmio_invalidate_full(struct 
>> intel_gt *gt)
>>       unsigned int num = 0;
>>       unsigned long flags;
>> -    if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
>> +    /*
>> +     * New platforms should not be added with catch-all-newer (>=)
>> +     * condition so that any later platform added triggers the below 
>> warning
>> +     * and in turn mandates a human cross-check of whether the 
>> invalidation
>> +     * flows have compatible semantics.
>> +     *
>> +     * For instance with the 11.00 -> 12.00 transition three out of five
>> +     * respective engine registers were moved to masked type. Then 
>> after the
>> +     * 12.00 -> 12.50 transition multi cast handling is required too.
>> +     */
>> +
>> +    if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50) &&
>> +        GRAPHICS_VER_FULL(i915) <= IP_VER(12, 55)) {
>>           regs = NULL;
>>           num = ARRAY_SIZE(xehp_regs);
>> -    } else if (GRAPHICS_VER(i915) == 12) {
>> +    } else if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 0) ||
>> +           GRAPHICS_VER_FULL(i915) == IP_VER(12, 10)) {
> 
> MTL support is lost? IP_VER(12, 70)

AFAIU Matt says MTL is still incomplete anyway, so that would be added 
in an explicit patch here.

> And again it looks for me inconsistent, some unknown platforms are 
> covered, for example 12.54, some not, for example 12.11.

.11 and .54 as hypotheticals? You suggest this instead:

	if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||
	    GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {
		regs = NULL;
		num = ARRAY_SIZE(xehp_regs);
	} else if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 0) ||
		   GRAPHICS_VER_FULL(i915) == IP_VER(12, 10)) {
		regs = gen12_regs;
		num = ARRAY_SIZE(gen12_regs);

?

It's fine by me if that covers all currently known platforms.

Regards,

Tvrtko

  reply	other threads:[~2023-01-10  9:16 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-06 10:38 [Intel-gfx] [PATCH v2] drm/i915: Do not cover all future platforms in TLB invalidation Tvrtko Ursulin
2023-01-06 16:08 ` Matt Roper
2023-01-09 12:24 ` [Intel-gfx] [PATCH v3] " Tvrtko Ursulin
2023-01-09 22:48   ` Matt Roper
2023-01-10  8:23   ` Andrzej Hajda
2023-01-10  9:16     ` Tvrtko Ursulin [this message]
2023-01-10  9:45       ` Andrzej Hajda

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