From: Chris Wilson <chris@chris-wilson.co.uk>
To: Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Subject: Re: [PATCH] drm/i915: rip out pre-production ilk cpu edp w/a
Date: Thu, 13 Sep 2012 13:38:05 +0100 [thread overview]
Message-ID: <6c3329$61hlba@orsmga002.jf.intel.com> (raw)
In-Reply-To: <1347534809-13341-1-git-send-email-daniel.vetter@ffwll.ch>
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On Thu, 13 Sep 2012 13:13:29 +0200, Daniel Vetter <daniel.vetter@ffwll.ch> wrote:
> While reading docs I've noticed that this special workaround to select
> the 1.6 GHz DP clock only applies to pre-production ilk machines.
> Since the registers we're touching here are rather undocumented and
> might be harmful on later chips, rip it out.
>
> For the Bspec reference of this w/a look in "vol4g CPU Display
> Registers [DevILK]", Section 4.1.7.1 "DP_A—DisplayPort A
> Control Register", "DP_PLL_Frequency_Select".
>
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
The spec definitely says DevILK-A, are we sure it got excised in
production machines? Once a w/a is implemented by the Windows driver
they have a tendency to linger...
So can you instead replace the w/a with a message to remind us
about the possibilty of failure of the PLL to change frequencies.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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next prev parent reply other threads:[~2012-09-13 12:38 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-09-13 11:13 [PATCH] drm/i915: rip out pre-production ilk cpu edp w/a Daniel Vetter
2012-09-13 12:38 ` Chris Wilson [this message]
2012-09-13 14:11 ` Daniel Vetter
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