From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Lionel Landwerlin <lionel.g.landwerlin@intel.com>,
Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Cc: paulo.r.zanoni@intel.com, intel-gfx@lists.freedesktop.org,
dri-devel@lists.freedesktop.org, thomas.hellstrom@intel.com,
chris.p.wilson@intel.com, daniel.vetter@intel.com,
christian.koenig@amd.com, matthew.auld@intel.com
Subject: Re: [Intel-gfx] [PATCH v3 3/3] drm/doc/rfc: VM_BIND uapi definition
Date: Thu, 23 Jun 2022 12:05:52 +0100 [thread overview]
Message-ID: <6d70cde9-f856-540a-b1d4-0325596b0c88@linux.intel.com> (raw)
In-Reply-To: <1874e47b-4337-5ac6-ebea-fca21ea1ba4c@intel.com>
On 23/06/2022 09:57, Lionel Landwerlin wrote:
> On 23/06/2022 11:27, Tvrtko Ursulin wrote:
>>>
>>> After a vm_unbind, UMD can re-bind to same VA range against an active
>>> VM.
>>> Though I am not sue with Mesa usecase if that new mapping is required
>>> for
>>> running GPU job or it will be for the next submission. But ensuring the
>>> tlb flush upon unbind, KMD can ensure correctness.
>>
>> Isn't that their problem? If they re-bind for submitting _new_ work
>> then they get the flush as part of batch buffer pre-amble.
>
> In the non sparse case, if a VA range is unbound, it is invalid to use
> that range for anything until it has been rebound by something else.
>
> We'll take the fence provided by vm_bind and put it as a wait fence on
> the next execbuffer.
>
> It might be safer in case of memory over fetching?
>
>
> TLB flush will have to happen at some point right?
>
> What's the alternative to do it in unbind?
Currently TLB flush happens from the ring before every BB_START and also
when i915 returns the backing store pages to the system.
For the former, I haven't seen any mention that for execbuf3 there are
plans to stop doing it? Anyway, as long as this is kept and sequence of
bind[1..N]+execbuf is safe and correctly sees all the preceding binds.
Hence about the alternative to doing it in unbind - first I think lets
state the problem that is trying to solve.
For instance is it just for the compute "append work to the running
batch" use case? I honestly don't remember how was that supposed to work
so maybe the tlb flush on bind was supposed to deal with that scenario?
Or you see a problem even for Mesa with the current model?
Regards,
Tvrtko
next prev parent reply other threads:[~2022-06-23 11:05 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-22 3:56 [Intel-gfx] [PATCH v3 0/3] drm/doc/rfc: i915 VM_BIND feature design + uapi Niranjana Vishwanathapura
2022-06-22 3:56 ` [Intel-gfx] [PATCH v3 1/3] drm/doc/rfc: VM_BIND feature design document Niranjana Vishwanathapura
2022-06-22 3:56 ` [Intel-gfx] [PATCH v3 2/3] drm/i915: Update i915 uapi documentation Niranjana Vishwanathapura
2022-06-22 3:56 ` [Intel-gfx] [PATCH v3 3/3] drm/doc/rfc: VM_BIND uapi definition Niranjana Vishwanathapura
2022-06-22 8:10 ` Tvrtko Ursulin
2022-06-22 15:12 ` Niranjana Vishwanathapura
2022-06-22 15:57 ` Tvrtko Ursulin
2022-06-22 16:44 ` Niranjana Vishwanathapura
2022-06-22 18:53 ` Niranjana Vishwanathapura
2022-06-23 8:27 ` Tvrtko Ursulin
2022-06-23 8:57 ` Lionel Landwerlin
2022-06-23 11:05 ` Tvrtko Ursulin [this message]
2022-06-23 12:41 ` Lionel Landwerlin
2022-06-23 21:05 ` Zeng, Oak
2022-06-24 8:32 ` Tvrtko Ursulin
2022-06-24 20:23 ` Zeng, Oak
2022-06-27 8:30 ` Tvrtko Ursulin
2022-06-27 18:58 ` Zeng, Oak
2022-06-28 8:58 ` Tvrtko Ursulin
2022-06-28 13:53 ` Zeng, Oak
2022-06-23 14:47 ` Niranjana Vishwanathapura
2022-06-23 9:28 ` Lionel Landwerlin
2022-06-23 14:43 ` Niranjana Vishwanathapura
2022-06-22 19:49 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/doc/rfc: i915 VM_BIND feature design + uapi Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-06-22 18:50 [Intel-gfx] [PATCH v4 0/3] " Niranjana Vishwanathapura
2022-06-22 18:50 ` [Intel-gfx] [PATCH v3 3/3] drm/doc/rfc: VM_BIND uapi definition Niranjana Vishwanathapura
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