From: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>
To: <John.C.Harrison@Intel.com>, <Intel-GFX@Lists.FreeDesktop.Org>
Cc: DRI-Devel@Lists.FreeDesktop.Org
Subject: Re: [Intel-gfx] [PATCH 3/8] drm/i915/guc: Better name for context id limit
Date: Tue, 22 Feb 2022 17:00:34 -0800 [thread overview]
Message-ID: <76086279-3214-7351-5825-bbf88f70b701@intel.com> (raw)
In-Reply-To: <20220217235207.930153-4-John.C.Harrison@Intel.com>
On 2/17/2022 3:52 PM, John.C.Harrison@Intel.com wrote:
> From: John Harrison <John.C.Harrison@Intel.com>
>
> The LRC descriptor pool is going away. So, stop using it as the limit
> for how many context ids are available.
I think this could be slightly reworded to make it clear that the
numbers are not changing. Maybe add something like "the desc pool is
sized based on the maximum numbers of contexts supported by the GuC, so
define that limit directly".
>
> While at it, also update a kzalloc(sizeof()*count) to be a
> kcalloc(count,size).
>
> Signed-off-by: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> ---
> drivers/gpu/drm/i915/gt/intel_context.c | 2 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 4 ++--
> .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 16 ++++++++--------
> drivers/gpu/drm/i915/gt/uc/selftest_guc.c | 2 +-
> 4 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_context.c b/drivers/gpu/drm/i915/gt/intel_context.c
> index 5d0ec7c49b6a..d87145b8fca0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_context.c
> +++ b/drivers/gpu/drm/i915/gt/intel_context.c
> @@ -400,7 +400,7 @@ intel_context_init(struct intel_context *ce, struct intel_engine_cs *engine)
> INIT_LIST_HEAD(&ce->guc_state.fences);
> INIT_LIST_HEAD(&ce->guc_state.requests);
>
> - ce->guc_id.id = GUC_INVALID_LRC_ID;
> + ce->guc_id.id = GUC_INVALID_CONTEXT_ID;
> INIT_LIST_HEAD(&ce->guc_id.link);
>
> INIT_LIST_HEAD(&ce->destroyed_link);
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index 6a4612a852e2..11099f0320ce 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -32,8 +32,8 @@
> #define GUC_CLIENT_PRIORITY_NORMAL 3
> #define GUC_CLIENT_PRIORITY_NUM 4
>
> -#define GUC_MAX_LRC_DESCRIPTORS 65535
> -#define GUC_INVALID_LRC_ID GUC_MAX_LRC_DESCRIPTORS
> +#define GUC_MAX_CONTEXT_ID 65535
> +#define GUC_INVALID_CONTEXT_ID GUC_MAX_CONTEXT_ID
>
> #define GUC_RENDER_ENGINE 0
> #define GUC_VIDEO_ENGINE 1
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> index 11bf56b5a266..ad784e8068c7 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
> @@ -354,12 +354,12 @@ request_to_scheduling_context(struct i915_request *rq)
>
> static inline bool context_guc_id_invalid(struct intel_context *ce)
> {
> - return ce->guc_id.id == GUC_INVALID_LRC_ID;
> + return ce->guc_id.id == GUC_INVALID_CONTEXT_ID;
> }
>
> static inline void set_context_guc_id_invalid(struct intel_context *ce)
> {
> - ce->guc_id.id = GUC_INVALID_LRC_ID;
> + ce->guc_id.id = GUC_INVALID_CONTEXT_ID;
> }
>
> static inline struct intel_guc *ce_to_guc(struct intel_context *ce)
> @@ -474,7 +474,7 @@ static struct guc_lrc_desc *__get_lrc_desc(struct intel_guc *guc, u32 index)
> {
> struct guc_lrc_desc *base = guc->lrc_desc_pool_vaddr;
>
> - GEM_BUG_ON(index >= GUC_MAX_LRC_DESCRIPTORS);
> + GEM_BUG_ON(index >= GUC_MAX_CONTEXT_ID);
>
> return &base[index];
> }
> @@ -483,7 +483,7 @@ static inline struct intel_context *__get_context(struct intel_guc *guc, u32 id)
> {
> struct intel_context *ce = xa_load(&guc->context_lookup, id);
>
> - GEM_BUG_ON(id >= GUC_MAX_LRC_DESCRIPTORS);
> + GEM_BUG_ON(id >= GUC_MAX_CONTEXT_ID);
>
> return ce;
> }
> @@ -494,7 +494,7 @@ static int guc_lrc_desc_pool_create(struct intel_guc *guc)
> int ret;
>
> size = PAGE_ALIGN(sizeof(struct guc_lrc_desc) *
> - GUC_MAX_LRC_DESCRIPTORS);
> + GUC_MAX_CONTEXT_ID);
> ret = intel_guc_allocate_and_map_vma(guc, size, &guc->lrc_desc_pool,
> (void **)&guc->lrc_desc_pool_vaddr);
> if (ret)
> @@ -2441,7 +2441,7 @@ static void __guc_context_sched_disable(struct intel_guc *guc,
> GUC_CONTEXT_DISABLE
> };
>
> - GEM_BUG_ON(guc_id == GUC_INVALID_LRC_ID);
> + GEM_BUG_ON(guc_id == GUC_INVALID_CONTEXT_ID);
>
> GEM_BUG_ON(intel_context_is_child(ce));
> trace_intel_context_sched_disable(ce);
> @@ -3840,7 +3840,7 @@ static bool __guc_submission_selected(struct intel_guc *guc)
>
> void intel_guc_submission_init_early(struct intel_guc *guc)
> {
> - guc->submission_state.num_guc_ids = GUC_MAX_LRC_DESCRIPTORS;
> + guc->submission_state.num_guc_ids = GUC_MAX_CONTEXT_ID;
> guc->submission_supported = __guc_submission_supported(guc);
> guc->submission_selected = __guc_submission_selected(guc);
> }
> @@ -3850,7 +3850,7 @@ g2h_context_lookup(struct intel_guc *guc, u32 desc_idx)
> {
> struct intel_context *ce;
>
> - if (unlikely(desc_idx >= GUC_MAX_LRC_DESCRIPTORS)) {
> + if (unlikely(desc_idx >= GUC_MAX_CONTEXT_ID)) {
> drm_err(&guc_to_gt(guc)->i915->drm,
> "Invalid desc_idx %u", desc_idx);
> return NULL;
> diff --git a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> index a115894d5896..1df71d0796ae 100644
> --- a/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/selftest_guc.c
> @@ -148,7 +148,7 @@ static int intel_guc_steal_guc_ids(void *arg)
> struct i915_request *spin_rq = NULL, *rq, *last = NULL;
> int number_guc_id_stolen = guc->number_guc_id_stolen;
>
> - ce = kzalloc(sizeof(*ce) * GUC_MAX_LRC_DESCRIPTORS, GFP_KERNEL);
> + ce = kcalloc(GUC_MAX_CONTEXT_ID, sizeof(*ce), GFP_KERNEL);
> if (!ce) {
> pr_err("Context array allocation failed\n");
> return -ENOMEM;
next prev parent reply other threads:[~2022-02-23 1:00 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-17 23:51 [Intel-gfx] [PATCH 0/8] Prep work for next GuC release John.C.Harrison
2022-02-17 23:52 ` [Intel-gfx] [PATCH 1/8] drm/i915/guc: Do not conflate lrc_desc with GuC id for registration John.C.Harrison
2022-02-18 21:13 ` Ceraolo Spurio, Daniele
2022-02-17 23:52 ` [Intel-gfx] [PATCH 2/8] drm/i915/guc: Add an explicit 'submission_initialized' flag John.C.Harrison
2022-02-18 21:18 ` Ceraolo Spurio, Daniele
2022-02-17 23:52 ` [Intel-gfx] [PATCH 3/8] drm/i915/guc: Better name for context id limit John.C.Harrison
2022-02-23 1:00 ` Ceraolo Spurio, Daniele [this message]
2022-02-17 23:52 ` [Intel-gfx] [PATCH 4/8] drm/i915/guc: Split guc_lrc_desc_pin apart John.C.Harrison
2022-02-23 1:04 ` Ceraolo Spurio, Daniele
2022-02-17 23:52 ` [Intel-gfx] [PATCH 5/8] drm/i915/guc: Move lrc desc setup to where it is needed John.C.Harrison
2022-02-23 1:12 ` Ceraolo Spurio, Daniele
2022-02-23 20:23 ` John Harrison
2022-02-24 2:03 ` Ceraolo Spurio, Daniele
2022-02-24 21:13 ` John Harrison
2022-02-17 23:52 ` [Intel-gfx] [PATCH 6/8] drm/i915/guc: Rename desc_idx to ctx_id John.C.Harrison
2022-02-23 1:14 ` Ceraolo Spurio, Daniele
2022-02-17 23:52 ` [Intel-gfx] [PATCH 7/8] drm/i915/guc: Drop obsolete H2G definitions John.C.Harrison
2022-02-23 1:19 ` Ceraolo Spurio, Daniele
2022-02-17 23:52 ` [Intel-gfx] [PATCH 8/8] drm/i915/guc: Fix potential invalid pointer dereferences when decoding G2Hs John.C.Harrison
2022-02-23 1:28 ` Ceraolo Spurio, Daniele
2022-02-18 5:29 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Prep work for next GuC release (rev2) Patchwork
2022-02-18 5:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-02-18 16:58 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2022-02-08 2:20 [Intel-gfx] [PATCH 0/8] Prep work for next GuC release John.C.Harrison
2022-02-08 2:20 ` [Intel-gfx] [PATCH 3/8] drm/i915/guc: Better name for context id limit John.C.Harrison
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