From: "Sripada, Radhakrishna" <radhakrishna.sripada@intel.com>
To: "Souza, Jose" <jose.souza@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "Nikula, Jani" <jani.nikula@intel.com>
Subject: Re: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values
Date: Tue, 29 Mar 2022 17:59:05 +0000 [thread overview]
Message-ID: <7963e5752f274089b07ae8ed45e9033e@intel.com> (raw)
In-Reply-To: <20220328191617.122838-1-jose.souza@intel.com>
> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of José
> Roberto de Souza
> Sent: Tuesday, March 29, 2022 12:46 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>
> Subject: [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Program
> PIPE_MBUS_DBOX_CTL with adl-p values
>
> From: Caz Yokoyama <caz.yokoyama@intel.com>
>
> B credits set by IFWI do not match with specification default, so here
> programming the right value.
>
> Also while at it, taking the oportunity to do a read-modify-write to
> not overwrite all other bits in this register that specification don't
> ask us to change.
>
> BSpec: 49213
> BSpec: 50343
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 3d2ff258f0a94..078ada041e1cd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1830,13 +1830,19 @@ static void icl_pipe_mbus_enable(struct intel_crtc
> *crtc, bool joined_mbus)
> enum pipe pipe = crtc->pipe;
> u32 val;
>
> + val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe));
> + val &= ~MBUS_DBOX_A_CREDIT_MASK;
> /* Wa_22010947358:adl-p */
> if (IS_ALDERLAKE_P(dev_priv))
> - val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
> MBUS_DBOX_A_CREDIT(4);
> + val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) :
> MBUS_DBOX_A_CREDIT(4);
> else
> - val = MBUS_DBOX_A_CREDIT(2);
> + val |= MBUS_DBOX_A_CREDIT(2);
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + val &= ~(MBUS_DBOX_BW_CREDIT_MASK |
> MBUS_DBOX_B_CREDIT_MASK);
> + if (IS_ALDERLAKE_P(dev_priv)) {
> + val |= MBUS_DBOX_BW_CREDIT(2);
> + val |= MBUS_DBOX_B_CREDIT(8);
> + } else if (DISPLAY_VER(dev_priv) >= 12) {
> val |= MBUS_DBOX_BW_CREDIT(2);
> val |= MBUS_DBOX_B_CREDIT(12);
> } else {
> --
> 2.35.1
next prev parent reply other threads:[~2022-03-29 17:59 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-28 19:16 [Intel-gfx] [PATCH v3 1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values José Roberto de Souza
2022-03-28 19:16 ` [Intel-gfx] [PATCH v3 2/3] drm/i915/display: Add HAS_MBUS_JOINING José Roberto de Souza
2022-03-28 19:16 ` [Intel-gfx] [PATCH v3 3/3] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL José Roberto de Souza
2022-03-29 21:23 ` Ville Syrjälä
2022-03-29 1:00 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values Patchwork
2022-03-29 1:04 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2022-03-29 1:22 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-29 3:45 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2022-03-29 17:59 ` Sripada, Radhakrishna [this message]
2022-03-29 18:14 ` [Intel-gfx] [PATCH v3 1/3] " Ville Syrjälä
2022-03-29 19:20 ` Souza, Jose
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