From: "Souza, Jose" <jose.souza@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
"Atwood, Matthew S" <matthew.s.atwood@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Navare, Manasi D" <manasi.d.navare@intel.com>,
"chris@chris-wilson.co.uk" <chris@chris-wilson.co.uk>
Subject: Re: [Intel-gfx] [PATCH] Revert "drm/i915/dp: Correctly advertise HBR3 for GEN11+"
Date: Thu, 2 Jul 2020 22:34:36 +0000 [thread overview]
Message-ID: <81c8ff248ea40be27ea51152fcef200c5f3c6a77.camel@intel.com> (raw)
In-Reply-To: <20200702221818.29094-1-matthew.s.atwood@intel.com>
On Thu, 2020-07-02 at 15:18 -0700, Matt Atwood wrote:
> The initial CI results did not include a TGL system which includes a
> panel that is having issues with patch. Revert while we triage.
>
> This reverts commit 680c45c767f63e35f063d3ea04f388a9f7ae7079.
Missing the Signed-off-by line also the commit references should follow this format "2850748ef876 ("drm/i915: Pull i915_vma_pin under the vm-
>mutex")".
Please CC me in the updated version.
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++----------
> 1 file changed, 17 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index a5ab405d3a12..d6295eb20b63 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -137,8 +137,6 @@ static const u8 valid_dsc_slicecount[] = {1, 2, 4};
> *
> * If a CPU or PCH DP output is attached to an eDP panel, this function
> * will return true, and false otherwise.
> - *
> - * This function is not safe to use prior to encoder type being set.
> */
> bool intel_dp_is_edp(struct intel_dp *intel_dp)
> {
> @@ -8159,6 +8157,8 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> intel_encoder->base.name))
> return false;
>
> + intel_dp_set_source_rates(intel_dp);
> +
> intel_dp->reset_link_params = true;
> intel_dp->pps_pipe = INVALID_PIPE;
> intel_dp->active_pipe = INVALID_PIPE;
> @@ -8174,22 +8174,28 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> */
> drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
> type = DRM_MODE_CONNECTOR_eDP;
> - intel_encoder->type = INTEL_OUTPUT_EDP;
> -
> - /* eDP only on port B and/or C on vlv/chv */
> - if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
> - IS_CHERRYVIEW(dev_priv)) &&
> - port != PORT_B && port != PORT_C))
> - return false;
> } else {
> type = DRM_MODE_CONNECTOR_DisplayPort;
> }
>
> - intel_dp_set_source_rates(intel_dp);
> -
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> intel_dp->active_pipe = vlv_active_pipe(intel_dp);
>
> + /*
> + * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
> + * for DP the encoder type can be set by the caller to
> + * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
> + */
> + if (type == DRM_MODE_CONNECTOR_eDP)
> + intel_encoder->type = INTEL_OUTPUT_EDP;
> +
> + /* eDP only on port B and/or C on vlv/chv */
> + if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
> + IS_CHERRYVIEW(dev_priv)) &&
> + intel_dp_is_edp(intel_dp) &&
> + port != PORT_B && port != PORT_C))
> + return false;
> +
> drm_dbg_kms(&dev_priv->drm,
> "Adding %s connector on [ENCODER:%d:%s]\n",
> type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
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next prev parent reply other threads:[~2020-07-02 22:35 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-02 22:18 [Intel-gfx] [PATCH] Revert "drm/i915/dp: Correctly advertise HBR3 for GEN11+" Matt Atwood
2020-07-02 22:34 ` Souza, Jose [this message]
2020-07-03 0:06 ` Manasi Navare
2020-07-02 22:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-07-02 23:15 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
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