From: Keith Packard <keithp@keithp.com>
To: Chris Wilson <chris@chris-wilson.co.uk>,
Daniel Vetter <daniel@ffwll.ch>, Takashi Iwai <tiwai@suse.de>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: Broken LVDS output at mode changes
Date: Thu, 29 Mar 2012 08:07:05 -0700 [thread overview]
Message-ID: <86d37vo38m.fsf@sumi.keithp.com> (raw)
In-Reply-To: <1333025081_141778@CP5-2952>
<#part sign=pgpmime>
On Thu, 29 Mar 2012 13:44:28 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> In conjunction with bits Power Sequence Progress field and Power Cycle
> Delay Active, this bit set to a one indicates that the panel is
> currently powered up or is currently in the power down sequence and it
> is unsafe to change the timing, port, and DPLL registers for the pipe or
> transcoder that is assigned to the panel output.
The theory was that as we don't touch the DPLL and only modify the
scaler, that the panel wouldn't care. I wonder what's confusing this one...
--
keith.packard@intel.com
next prev parent reply other threads:[~2012-03-29 15:07 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-28 13:29 Broken LVDS output at mode changes Takashi Iwai
2012-03-29 12:16 ` Daniel Vetter
2012-03-29 12:44 ` Chris Wilson
2012-03-29 12:51 ` Daniel Vetter
2012-03-29 12:55 ` Takashi Iwai
2012-03-29 15:07 ` Keith Packard [this message]
2012-03-29 16:12 ` Takashi Iwai
2012-03-29 16:57 ` Keith Packard
2012-03-29 18:02 ` Takashi Iwai
2012-03-30 4:27 ` Keith Packard
2012-03-30 16:56 ` Jesse Barnes
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