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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Matt Roper <matthew.d.roper@intel.com>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Handle cdclk crawling flag in standard manner
Date: Thu, 08 Jul 2021 13:27:53 +0300	[thread overview]
Message-ID: <871r896qxi.fsf@intel.com> (raw)
In-Reply-To: <20210707234206.2002849-1-matthew.d.roper@intel.com>

On Wed, 07 Jul 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> The 'has_cdclk_crawl' field in our device info structure is a boolean
> flag and doesn't need a whole u8.  Add it as another 1-bit feature flag
> and move it to the display section.  While we're at it, replace the
> has_cdclk_crawl() function with a macro for consistency with our
> handling of other feature flags.
>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Thanks for fixing this.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 9 ++-------
>  drivers/gpu/drm/i915/i915_drv.h            | 1 +
>  drivers/gpu/drm/i915/i915_pci.c            | 2 +-
>  drivers/gpu/drm/i915/intel_device_info.h   | 3 +--
>  4 files changed, 5 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 613ffcc68eba..df2d8ce4a12f 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1548,11 +1548,6 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
>  	dev_priv->cdclk.hw.vco = vco;
>  }
>  
> -static bool has_cdclk_crawl(struct drm_i915_private *i915)
> -{
> -	return INTEL_INFO(i915)->has_cdclk_crawl;
> -}
> -
>  static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
>  {
>  	int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->cdclk.hw.ref);
> @@ -1649,7 +1644,7 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
>  		return;
>  	}
>  
> -	if (has_cdclk_crawl(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
> +	if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->cdclk.hw.vco > 0 && vco > 0) {
>  		if (dev_priv->cdclk.hw.vco != vco)
>  			adlp_cdclk_pll_crawl(dev_priv, vco);
>  	} else if (DISPLAY_VER(dev_priv) >= 11 || IS_CANNONLAKE(dev_priv)) {
> @@ -1857,7 +1852,7 @@ static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
>  {
>  	int a_div, b_div;
>  
> -	if (!has_cdclk_crawl(dev_priv))
> +	if (!HAS_CDCLK_CRAWL(dev_priv))
>  		return false;
>  
>  	/*
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6dff4ca01241..30129ca4049a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1647,6 +1647,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>  
>  #define HAS_DP_MST(dev_priv)	(INTEL_INFO(dev_priv)->display.has_dp_mst)
>  
> +#define HAS_CDCLK_CRAWL(dev_priv)	 (INTEL_INFO(dev_priv)->display.has_cdclk_crawl)
>  #define HAS_DDI(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_ddi)
>  #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->display.has_fpga_dbg)
>  #define HAS_PSR(dev_priv)		 (INTEL_INFO(dev_priv)->display.has_psr)
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index a7bfdd827bc8..b2deb039f954 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -984,8 +984,8 @@ static const struct intel_device_info adl_p_info = {
>  	GEN12_FEATURES,
>  	XE_LPD_FEATURES,
>  	PLATFORM(INTEL_ALDERLAKE_P),
> -	.has_cdclk_crawl = 1,
>  	.require_force_probe = 1,
> +	.display.has_cdclk_crawl = 1,
>  	.display.has_modular_fia = 1,
>  	.display.has_psr_hw_tracking = 0,
>  	.platform_engine_mask =
> diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
> index b326aff65cd6..3582253ee05b 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.h
> +++ b/drivers/gpu/drm/i915/intel_device_info.h
> @@ -141,6 +141,7 @@ enum intel_ppgtt_type {
>  #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
>  	/* Keep in alphabetical order */ \
>  	func(cursor_needs_physical); \
> +	func(has_cdclk_crawl); \
>  	func(has_dmc); \
>  	func(has_ddi); \
>  	func(has_dp_mst); \
> @@ -185,8 +186,6 @@ struct intel_device_info {
>  
>  	u8 abox_mask;
>  
> -	u8 has_cdclk_crawl;  /* does support CDCLK crawling */
> -
>  #define DEFINE_FLAG(name) u8 name:1
>  	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
>  #undef DEFINE_FLAG

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

      parent reply	other threads:[~2021-07-08 10:28 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-07 23:42 [Intel-gfx] [PATCH] drm/i915: Handle cdclk crawling flag in standard manner Matt Roper
2021-07-08  1:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-07-08  6:47 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-07-08 14:53   ` Matt Roper
2021-07-08 10:27 ` Jani Nikula [this message]

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