From: Jani Nikula <jani.nikula@linux.intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values
Date: Mon, 21 Mar 2022 14:48:44 +0200 [thread overview]
Message-ID: <874k3rlbdf.fsf@intel.com> (raw)
In-Reply-To: <20220318195522.456180-1-jose.souza@intel.com>
On Fri, 18 Mar 2022, José Roberto de Souza <jose.souza@intel.com> wrote:
> From: Caz Yokoyama <caz.yokoyama@intel.com>
>
> B credits set by IFWI do not match with specification default, so here
> programming the right value.
>
> Also while at it, taking the oportunity to do a read-modify-write to
> all other bit in this register that specification don't ask us to
> change.
>
> BSpec: 49213
> BSpec: 50343
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Signed-off-by: Caz Yokoyama <caz.yokoyama@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7cd586d280883..2e85ae575423a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1825,15 +1825,20 @@ static void icl_pipe_mbus_enable(struct intel_crtc *crtc, bool joined_mbus)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum pipe pipe = crtc->pipe;
> - u32 val;
> + u32 val = intel_de_read(dev_priv, PIPE_MBUS_DBOX_CTL(pipe));
Please don't do functional stuff in variable initialization.
BR,
Jani.
>
> + val &= ~MBUS_DBOX_A_CREDIT_MASK;
> /* Wa_22010947358:adl-p */
> if (IS_ALDERLAKE_P(dev_priv))
> - val = joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);
> + val |= joined_mbus ? MBUS_DBOX_A_CREDIT(6) : MBUS_DBOX_A_CREDIT(4);
> else
> - val = MBUS_DBOX_A_CREDIT(2);
> + val |= MBUS_DBOX_A_CREDIT(2);
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + val &= ~(MBUS_DBOX_BW_CREDIT_MASK | MBUS_DBOX_B_CREDIT_MASK);
> + if (IS_ALDERLAKE_P(dev_priv)) {
> + val |= MBUS_DBOX_BW_CREDIT(2);
> + val |= MBUS_DBOX_B_CREDIT(8);
> + } else if (DISPLAY_VER(dev_priv) >= 12) {
> val |= MBUS_DBOX_BW_CREDIT(2);
> val |= MBUS_DBOX_B_CREDIT(12);
> } else {
--
Jani Nikula, Intel Open Source Graphics Center
prev parent reply other threads:[~2022-03-21 12:49 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-18 19:55 [Intel-gfx] [PATCH 1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values José Roberto de Souza
2022-03-18 19:55 ` [Intel-gfx] [PATCH 2/3] drm/i915/display: Add HAS_MBUS_JOINING José Roberto de Souza
2022-03-18 21:31 ` Ville Syrjälä
2022-03-18 19:55 ` [Intel-gfx] [PATCH 3/3] drm/i915/display/adlp: Fix programing of PIPE_MBUS_DBOX_CTL José Roberto de Souza
2022-03-18 21:28 ` Ville Syrjälä
2022-03-22 17:07 ` Souza, Jose
2022-03-18 20:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/3] drm/i915/display: Program PIPE_MBUS_DBOX_CTL with adl-p values Patchwork
2022-03-18 20:55 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-03-21 12:48 ` Jani Nikula [this message]
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