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From: Jani Nikula <jani.nikula@intel.com>
To: Vandita Kulkarni <vandita.kulkarni@intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] Revert "drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping"
Date: Tue, 09 Nov 2021 15:57:30 +0200	[thread overview]
Message-ID: <877ddh5t4l.fsf@intel.com> (raw)
In-Reply-To: <20211109120428.15211-1-vandita.kulkarni@intel.com>

On Tue, 09 Nov 2021, Vandita Kulkarni <vandita.kulkarni@intel.com> wrote:
> This reverts commit 991d9557b0c457fb92bc49ddde24a7d9ce6144a8.
> The Bspec was updated recently with the pll ungate sequence
> similar to that of icl dsi enable sequence.
> Hence reverting.
>
> Bspec:49187

Please add a space after : in the Bspec tag, and please add a Fixes: tag
while applying.

>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c | 10 ++--------
>  1 file changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 2337c0b54586..edc38fbd2545 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -698,10 +698,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder,
>  	intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
>  
>  	for_each_dsi_phy(phy, intel_dsi->phys) {
> -		if (DISPLAY_VER(dev_priv) >= 12)
> -			val |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> -		else
> -			val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> +		val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
>  	}
>  	intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
>  
> @@ -1137,8 +1134,6 @@ static void
>  gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>  			      const struct intel_crtc_state *crtc_state)
>  {
> -	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> -
>  	/* step 4a: power up all lanes of the DDI used by DSI */
>  	gen11_dsi_power_up_lanes(encoder);
>  
> @@ -1164,8 +1159,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>  	gen11_dsi_configure_transcoder(encoder, crtc_state);
>  
>  	/* Step 4l: Gate DDI clocks */
> -	if (DISPLAY_VER(dev_priv) == 11)
> -		gen11_dsi_gate_clocks(encoder);
> +	gen11_dsi_gate_clocks(encoder);
>  }
>  
>  static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)

-- 
Jani Nikula, Intel Open Source Graphics Center

  parent reply	other threads:[~2021-11-09 13:57 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-11-09 12:04 [Intel-gfx] [PATCH] Revert "drm/i915/tgl/dsi: Gate the ddi clocks after pll mapping" Vandita Kulkarni
2021-11-09 13:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-11-09 13:57 ` Jani Nikula [this message]
2021-11-10 10:31   ` [Intel-gfx] [PATCH] " Jani Nikula
2021-11-09 15:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork

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