From: Jani Nikula <jani.nikula@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Animesh Manna <animesh.manna@intel.com>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dg2: UHBR tables added for pll programming
Date: Mon, 30 Aug 2021 13:25:13 +0300 [thread overview]
Message-ID: <877dg3cjqu.fsf@intel.com> (raw)
In-Reply-To: <20210827103843.527-1-jani.nikula@intel.com>
On Fri, 27 Aug 2021, Jani Nikula <jani.nikula@intel.com> wrote:
> From: Animesh Manna <animesh.manna@intel.com>
>
> UHBR modes has higher link rate and added new values for programming
> mpll of SNPS phy. No change in sequence, only the pll parameters
> are different for UHBR modes.
>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Pushed, thanks for the patch.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/display/intel_snps_phy.c | 147 ++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 4 +
> 2 files changed, 151 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> index 58ec2467ad66..2405f70d82de 100644
> --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
> @@ -171,11 +171,81 @@ static const struct intel_mpllb_state dg2_dp_hbr3_100 = {
> REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> };
>
> +static const struct intel_mpllb_state dg2_dp_uhbr10_100 = {
> + .clock = 1000000,
> + .ref_control =
> + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
> + .mpllb_cp =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 4) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 21) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> + .mpllb_div =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
> + .mpllb_div2 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 368),
> + .mpllb_fracn1 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> +
> + /*
> + * SSC will be enabled, DP UHBR has a minimum SSC requirement.
> + */
> + .mpllb_sscen =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 58982),
> + .mpllb_sscstep =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101),
> +};
> +
> +static const struct intel_mpllb_state dg2_dp_uhbr13_100 = {
> + .clock = 1350000,
> + .ref_control =
> + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
> + .mpllb_cp =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> + .mpllb_div =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
> + .mpllb_div2 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508),
> + .mpllb_fracn1 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> +
> + /*
> + * SSC will be enabled, DP UHBR has a minimum SSC requirement.
> + */
> + .mpllb_sscen =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626),
> + .mpllb_sscstep =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737),
> +};
> +
> static const struct intel_mpllb_state * const dg2_dp_100_tables[] = {
> &dg2_dp_rbr_100,
> &dg2_dp_hbr1_100,
> &dg2_dp_hbr2_100,
> &dg2_dp_hbr3_100,
> + &dg2_dp_uhbr10_100,
> + &dg2_dp_uhbr13_100,
> NULL,
> };
>
> @@ -284,11 +354,88 @@ static const struct intel_mpllb_state dg2_dp_hbr3_38_4 = {
> REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 61440),
> };
>
> +static const struct intel_mpllb_state dg2_dp_uhbr10_38_4 = {
> + .clock = 1000000,
> + .ref_control =
> + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> + .mpllb_cp =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 26) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> + .mpllb_div =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2),
> + .mpllb_div2 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 488),
> + .mpllb_fracn1 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 3),
> + .mpllb_fracn2 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 27306),
> +
> + /*
> + * SSC will be enabled, DP UHBR has a minimum SSC requirement.
> + */
> + .mpllb_sscen =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 76800),
> + .mpllb_sscstep =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 129024),
> +};
> +
> +static const struct intel_mpllb_state dg2_dp_uhbr13_38_4 = {
> + .clock = 1350000,
> + .ref_control =
> + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 1),
> + .mpllb_cp =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 56) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127),
> + .mpllb_div =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3),
> + .mpllb_div2 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 670),
> + .mpllb_fracn1 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1),
> + .mpllb_fracn2 =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36864),
> +
> + /*
> + * SSC will be enabled, DP UHBR has a minimum SSC requirement.
> + */
> + .mpllb_sscen =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) |
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 103680),
> + .mpllb_sscstep =
> + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 174182),
> +};
> +
> static const struct intel_mpllb_state * const dg2_dp_38_4_tables[] = {
> &dg2_dp_rbr_38_4,
> &dg2_dp_hbr1_38_4,
> &dg2_dp_hbr2_38_4,
> &dg2_dp_hbr3_38_4,
> + &dg2_dp_uhbr10_38_4,
> + &dg2_dp_uhbr13_38_4,
> NULL,
> };
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8d4cf1e203ab..40943dd5e0db 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2237,10 +2237,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
>
> #define SNPS_PHY_MPLLB_DIV(phy) _MMIO_SNPS(phy, 0x168004)
> #define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
> +#define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
> #define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
> #define SNPS_PHY_MPLLB_V2I REG_GENMASK(27, 26)
> #define SNPS_PHY_MPLLB_FREQ_VCO REG_GENMASK(25, 24)
> +#define SNPS_PHY_MPLLB_DIV_MULTIPLIER REG_GENMASK(23, 16)
> #define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
> +#define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
> +#define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
> #define SNPS_PHY_MPLLB_TX_CLK_DIV REG_GENMASK(7, 5)
>
> #define SNPS_PHY_MPLLB_FRACN1(phy) _MMIO_SNPS(phy, 0x168008)
--
Jani Nikula, Intel Open Source Graphics Center
prev parent reply other threads:[~2021-08-30 10:25 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-27 10:38 [Intel-gfx] [PATCH] drm/i915/dg2: UHBR tables added for pll programming Jani Nikula
2021-08-27 11:21 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2021-08-27 15:03 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2021-08-30 10:25 ` Jani Nikula [this message]
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