Re: [PATCH] drm/i915/icl: restore WaEnableFloatBlendOptimization

[Mika Kuoppala <mika.kuoppala@linux.intel.com>]

Talha writes:

> From: talha nassar <talha.nassar@intel.com>
>
> Enables blend optimization for floating point RTs
>
> This restores the workaround that was reverted in c358514ba8da
> ("Revert "drm/i915/icl: WaEnableFloatBlendOptimization"").
>
> The revert was due to the register write seemingly not sticking,
> but the HW team has confirmed that this is because the
> register is WO and that the workaround is indeed required.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=107338
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: talha nassar <talha.nassar@intel.com>

Could you add HSDES# if you have it? eg.

References: HSDES# 12345679000

Thanks,
-Mika

> ---
>  drivers/gpu/drm/i915/i915_reg.h          | 3 +++
>  drivers/gpu/drm/i915/intel_workarounds.c | 4 ++++
>  2 files changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0796526..5c43720 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2795,6 +2795,9 @@ enum i915_power_well_id {
>  #define GEN6_RCS_PWR_FSM _MMIO(0x22ac)
>  #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4)
>  
> +#define GEN10_CACHE_MODE_SS			_MMIO(0xe420)
> +#define   FLOAT_BLEND_OPTIMIZATION_ENABLE	(1 << 4)
> +
>  /* Fuse readout registers for GT */
>  #define HSW_PAVP_FUSE1			_MMIO(0x911C)
>  #define   HSW_F1_EU_DIS_SHIFT		16
> diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
> index 7a86180..bc614f0 100644
> --- a/drivers/gpu/drm/i915/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/intel_workarounds.c
> @@ -532,6 +532,10 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine)
>  	if (IS_ICL_REVID(i915, ICL_REVID_A0, ICL_REVID_A0))
>  		WA_SET_BIT_MASKED(GEN11_COMMON_SLICE_CHICKEN3,
>  				  GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC);
> +
> +	/* WaEnableFloatBlendOptimization:icl */
> +	WA_SET_BIT_MASKED(GEN10_CACHE_MODE_SS,
> +			  FLOAT_BLEND_OPTIMIZATION_ENABLE);
>  }
>  
>  void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
> -- 
> 2.7.4
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