Re: [PATCH v3] drm/i915: BXT DDI PHY sequence BUN

[Jani Nikula <jani.nikula@intel.com>]

On Thu, 31 Mar 2016, Vandana Kannan <vandana.kannan@intel.com> wrote:
> According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register needs to be
> checked to ensure that the register is in accessible state.
> Also, based on a BSpec update, changing the timeout value to
> check iphypwrgood, from 10ms to wait for up to 100us.
>
> v2: [Ville] use wait_for_us instead of the atomic call.
> v3: [Jani/Imre] read register only once
>
> Signed-off-by: Vandana Kannan <vandana.kannan@intel.com>
> Reported-by: Philippe Lecluse <Philippe.Lecluse@intel.com>
> Cc: Deak, Imre <imre.deak@intel.com>
> Cc: Nikula, Jani <jani.nikula@intel.com>

Acked-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  1 +
>  drivers/gpu/drm/i915/intel_ddi.c | 13 +++++++++++--
>  2 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7dfc400..9a02bfc 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells {
>  #define _PORT_CL1CM_DW0_A		0x162000
>  #define _PORT_CL1CM_DW0_BC		0x6C000
>  #define   PHY_POWER_GOOD		(1 << 16)
> +#define   PHY_RESERVED			(1 << 7)
>  #define BXT_PORT_CL1CM_DW0(phy)		_BXT_PHY((phy), _PORT_CL1CM_DW0_BC, \
>  							_PORT_CL1CM_DW0_A)
>  
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 62de9f4..4a8f504 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2669,9 +2669,18 @@ static void broxton_phy_init(struct drm_i915_private *dev_priv,
>  	val |= GT_DISPLAY_POWER_ON(phy);
>  	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
>  
> -	/* Considering 10ms timeout until BSpec is updated */
> -	if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
> +	/*
> +	 * The PHY registers start out inaccessible and respond to reads with
> +	 * all 1s.  Eventually they become accessible as they power up, then
> +	 * the reserved bit will give the default 0.  Poll on the reserved bit
> +	 * becoming 0 to find when the PHY is accessible.
> +	 * HW team confirmed that the time to reach phypowergood status is
> +	 * anywhere between 50 us and 100us.
> +	 */
> +	if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
> +		(PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
>  		DRM_ERROR("timeout during PHY%d power on\n", phy);
> +	}
>  
>  	for (port =  (phy == DPIO_PHY0 ? PORT_B : PORT_A);
>  	     port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {

-- 
Jani Nikula, Intel Open Source Technology Center
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